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touch key flash type 8-bit mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 revision: v1.20 date: ???? st 10 ? 2012 ???? st 10 ? 2012
rev. 1.20 2 ???? st 10 ? 2012 rev. 1.20 3 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver table of contents eates cpu feat ? res ......................................................................................................................... 7 peripheral feat ? res ................................................................................................................. 7 selection table ................................................................................................. 8 block dia?ram .................................................................................................. 9 pin ?ssi?nment ........... ..................................................................................... 9 pin description .......... ..................................................................................... 11 bs85b12-3 ............................................................................................................................. 11 bs85c20-3 ............. ............................................................................................................... 13 bs85c20-5 ............. ............................................................................................................... 17 ?bsol?te maxim?m ratin?s .......................................................................... 20 d.c. characteristics ....................................................................................... 21 ?.c. characteristics ....................................................................................... 22 power-on reset characteristics ........... ........................................................ 23 oscillator temperat?re/freq?ency characteristics ................................... 24 system ?rchitect?re ...................................................................................... 26 clockin ? and pipelinin ? ......................................................................................................... 26 pro ? ram co ? nter ................................................................................................................... 27 stack ..................................................................................................................................... 28 ? rithmetic and lo ? ic unit C ? lu ........................................................................................... 28 flash pro?ram memory ................................................................................. 29 str ? ct ? re ................................................................................................................................ 29 special vectors ..................................................................................................................... 29 look- ? p table ............. ........................................................................................................... 29 table pro ? ram example ........................................................................................................ 30 in circ ? it pro ? rammin ? ......................................................................................................... 31 r?m data memory ......................................................................................... 32 str ? ct ? re ................................................................................................................................ 32 special f?nction re?ister description ........................................................ 32 indirect ? ddressin ? re ? isters C i ? r0 ? i ? r1 ......................................................................... 32 memory pointers C mp0 ? mp1 .............................................................................................. 33 bank pointer C bp ................................................................................................................. 35 ? cc ? m ? lator C ? cc ............................................................................................................... 36 pro ? ram co ? nter low re ? ister C pcl .................................................................................. 36 look- ? p table re ? isters C tblp ? tbhp ? tblh ..................................................................... 36 stat ? s re ? ister C st ? tus .................................................................................................... 36
rev. 1.20 2 ????st 10? 2012 rev. 1.20 3 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver eeprom data memory ........... ....................................................................... 38 eeprom data memory str ? ct ? re ........................................................................................ 38 readin ? data from the eeprom ......................................................................................... 40 writin ? data to the eeprom ................................................................................................ 40 write protection ..................................................................................................................... 40 eeprom interr ? pt ............. ................................................................................................... 41 pro ? rammin ? considerations ............. ................................................................................... 41 pro ? rammin ? examples ........................................................................................................ 41 oscillator ........................................................................................................ 42 oscillator overview ............. .................................................................................................. 42 system clock confgurations ................................................................................................ 42 internal hi ? h speed rc oscillator C hirc ........................................................................... 42 external 32.768khz crystal oscillator C lxt (bs85c20-5 only) .......................................... 43 lxt oscillator low power f ? nction (bs85c20-5 only) ........................................................ 44 internal low speed rc oscillator C lirc ............................................................................. 44 operating modes and system clocks ......................................................... 44 system clocks ...................................................................................................................... 44 control re ? ister .................................................................................................................... 46 system operation modes ...................................................................................................... 47 operatin ? mode switchin ? .................................................................................................... 48 norm ? l mode to slow mode switchin ? ........................................................................... 49 slow mode to norm ? l mode switchin ? ........................................................................... 49 enterin ? the sleep mode .................................................................................................... 49 enterin ? the idle0 mode ...................................................................................................... 50 enterin ? the idle1 mode ...................................................................................................... 50 standby c ? rrent considerations ........................................................................................... 50 wake- ? p ................................................................................................................................ 51 pro ? rammin ? considerations ............. ................................................................................... 51 watchdog timer ........... .................................................................................. 52 watchdo ? timer clock so ? rce .............................................................................................. 52 watchdo ? timer control re ? ister ............. ............................................................................ 52 watchdo ? timer operation ................................................................................................... 53 reset and initialisation .................................................................................. 54 reset f ? nctions ............. ....................................................................................................... 54 reset initial conditions ......................................................................................................... 55 input/output ports ......................................................................................... 59 i/o re ? ister list .................................................................................................................... 59 p ? ll-hi ? h resistors ................................................................................................................ 60 port ? wake- ? p ............. ........................................................................................................ 60 i/o port control re ? ister ....................................................................................................... 61 pin re-mappin ? f ? nctions .................................................................................................... 61 i/o pin str ? ct ? res .................................................................................................................. 66 pro ? rammin ? considerations ............. ................................................................................... 66
rev. 1.20 4 ???? st 10 ? 2012 rev. 1.20 5 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver timer modules C tm .......... ............................................................................ 67 introd ? ction ........................................................................................................................... 67 tm operation ............. ........................................................................................................... 67 tm clock so ? rce ............. ...................................................................................................... 68 tm interr ? pts ......................................................................................................................... 68 tm external pins ................................................................................................................... 68 tm inp ? t/o ? tp ? t pin control re ? isters ............. .................................................................... 69 pro ? rammin ? considerations ............. ................................................................................... 72 compact type tm C ctm .............................................................................. 73 compact tm operation ......................................................................................................... 73 compact type tm re ? ister description ................................................................................ 74 compact type tm operatin ? modes .................................................................................... 77 compare match o ? tp ? t mode ............................................................................................... 77 timer/co ? nter mode ............................................................................................................. 79 pwm o ? tp ? t mode ............. ................................................................................................... 80 standard type tm C stm .......... .................................................................... 82 standard tm operation ............. ............................................................................................ 82 standard type tm re ? ister description ............................................................................... 83 standard type tm operatin ? modes .................................................................................... 87 compare match o ? tp ? t mode ............................................................................................... 87 timer/co ? nter mode ............................................................................................................. 88 pwm o ? tp ? t mode ............. ................................................................................................... 89 sin ? le p ? lse mode ................................................................................................................ 91 capt ? re inp ? t mode .............................................................................................................. 93 enhanced type tm C etm ........... .................................................................. 94 enhanced tm operation ....................................................................................................... 94 enhanced type tm re ? ister description .............................................................................. 95 enhanced type tm operatin ? modes ................................................................................. 100 compare o ? tp ? t mode ............. ........................................................................................... 101 timer/co ? nter mode ........................................................................................................... 105 pwm o ? tp ? t mode ............. ................................................................................................. 105 sin ? le p ? lse o ? tp ? t mode ................................................................................................... 111 capt ? re inp ? t mode ............................................................................................................. 113 touch key function ..................................................................................... 115 to ? ch key str ? ct ? re ............................................................................................................. 115 touch key register defnition .............................................................................................. 115 to ? ch key operation ............................................................................................................ 119 to ? ch key interr ? pt ............................................................................................................. 120 pro ? rammin ? considerations ............. ................................................................................. 120 serial interface module C sim ..................................................................... 121 spi interface ....................................................................................................................... 121 spi re ? isters ............. ......................................................................................................... 122 spi comm ? nication ............................................................................................................ 125
rev. 1.20 4 ????st 10? 2012 rev. 1.20 5 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver i 2 c interface ............ ............................................................................................................ 127 i 2 c re ? isters ....................................................................................................................... 128 i 2 c b ? s comm ? nication ...................................................................................................... 132 i 2 c b ? s start si ? nal ............................................................................................................. 132 slave ? ddress ..................................................................................................................... 133 i 2 c b ? s read/write si ? nal .................................................................................................. 133 i 2 c b ? s slave ? ddress ? cknowled ? e si ? nal ....................................................................... 134 i 2 c b ? s data and ? cknowled ? e si ? nal ............ ................................................................... 134 i 2 c time-o ? t control ............................................................................................................ 135 peripheral clock output ........... ................................................................... 136 peripheral clock operation ............. .................................................................................... 136 interrupts ...................................................................................................... 137 interr ? pt re ? isters ............................................................................................................... 137 interr ? pt re ? ister contents ............. .................................................................................... 138 interr ? pt operation .............................................................................................................. 144 external interr ? pt ............. .................................................................................................... 146 m ? lti-f ? nction interr ? pt ........................................................................................................ 146 time base interr ? pts ........................................................................................................... 146 external peripheral interr ? pt ............. .................................................................................. 148 lvd interr ? pt ....................................................................................................................... 149 tm interr ? pts ....................................................................................................................... 149 eeprom interr ? pt ............. ................................................................................................. 149 to ? ch key interr ? pts ............. .............................................................................................. 149 sim interr ? pt ....................................................................................................................... 150 interr ? pt wake- ? p f ? nction ................................................................................................. 150 pro ? rammin ? considerations ............. ................................................................................. 150 low voltage detector C lvd .......... ............................................................. 151 lvd re ? ister ............. .......................................................................................................... 151 lvd operation ..................................................................................................................... 152 lcd driver C scom and sseg function ................................................... 152 lcd operation ............. ....................................................................................................... 152 lcd bias control ................................................................................................................ 154 lcd driver re ? isters ............. ............................................................................................. 154 led driver .................................................................................................... 156 led driver operation .......................................................................................................... 156 led driver re ? isters ............ .............................................................................................. 156 application circuits ........... .......................................................................... 157 instruction set .............................................................................................. 158 introd ? ction ......................................................................................................................... 158 instr ? ction timin ? ................................................................................................................ 158 movin ? and transferrin ? data ............................................................................................. 158 ? rithmetic operations .......................................................................................................... 158 lo ? ical and rotate operation ............................................................................................. 159
rev. 1.20 6 ???? st 10 ? 2012 rev. 1.20 7 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver branches and control transfer ........................................................................................... 159 bit operations ..................................................................................................................... 159 table read operations ....................................................................................................... 159 other operations ............. .................................................................................................... 159 instruction set summary .......... .................................................................. 160 table conventions ............................................................................................................... 160 instruction defnition ................................................................................... 162 package information ................................................................................... 171 24-pin skdip (300mil) o ? tline dimensions ............. ........................................................... 171 24-pin sop (300mil) o ? tline dimensions ........................................................................... 174 24-pin ssop (150mil) o ? tline dimensions ......................................................................... 175 28-pin skdip (300mil) o ? tline dimensions ............. ........................................................... 176 28-pin sop (300mil) o ? tline dimensions ........................................................................... 177 28-pin ssop (150mil) o ? tline dimensions ......................................................................... 178 44-pin qfp (10mm10mm) o ? tline dimensions ................................................................ 179 product tape and reel specifcations ....................................................... 180 reel dimensions ................................................................................................................. 180 carrier tape dimensions ..................................................................................................... 181
rev. 1.20 6 ????st 10? 2012 rev. 1.20 7 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver features cpu features ? operating v oltage: f sys = 8mhz: v lvr ~5.5v f sys = 12mhz: 2.7v~5.5v f sys = 16mhz: 4.5v~5.5v ? power down and wake-up functions to reduce power consumption ? oscillator types: external 32.768khz crystal C lxt internal rc C hirc internal 32khz rc C lirc ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? up to 8 subroutine nesting levels ? bit manipulation instruction peripheral features ? fully integrated 12 or 20 touch key functions -- require no external components ? flash program memory: 2k 15 or 4k 15 ? ram data memory: 256 8 or 384 8 ? eeprom memory: 64 8 or 128 8 ? watchdog t imer function ? up to 38 bidirectional i/o lines ? two or three t imer modules ? dual t ime-base functions for generation of fxed time interrupt signals ? i 2 c and spi interfaces ? low voltage reset function ? software controlled 4 14 or 4 22 lcd driver with 1/3 bias ? software controlled 6 8 or 8 14 led driver
rev. 1.20 8 ???? st 10 ? 2012 rev. 1.20 9 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver general description these devices are a series of flash memory type 8-bit high performance risc architecture microcontrollers with fully integrated touch key functions and lcd/led drivers. w ith all touch key functions provided internally and with the convenience of flash memory multi-programming features, this device range has all the features to of fer designers a reliable and easy means of implementing t ouch keys within their products applications. the touch key functions are fully integrated completely eliminating the need for external components. the inclusion of both lcd and led driver functions allows for easy and cost ef fective solutions in applications that require to interface to these display types. in addition to the fash program memory , other memory includes an area of ram data memory as well as an area of eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. protective features such as an internal w atchdog t imer, low v oltage reset and low v oltage detector functions coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a choice of oscill ator functions are provided including a fully integra ted system oscillator which requires no e xternal c omponents for i ts i mplementation. t he a bility t o ope rate a nd swi tch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. easy communication with the outside world is provided using the internal i2c and spi interfaces, while the inclusion of fexible i/o programming features, t imer modules and many other features further enhance device functionality and fexibility. these touch key devices will find excellent use in a huge range of modern t ouch key product applications such as instrumentatio n, household appliances, electronic ally controlled tools to name but a few. selection table part no. internal clock vdd system clock program memory data memory data eeprom i/o oscillator type timer module touch key lcd driver led driver spi/ i 2 c stack package bs85b12-3 8mhz 12mhz 16mhz v lvr ~ 5.5v 8mhz ~ 16mhz 2k15 2568 648 22 hirc lirc 2 12 414 68 1 4 24/28skdip /sop 24/28ssop bs85c20-3 8mhz 12mhz 16mhz v lvr ~ 5.5v 8mhz ~ 16mhz 4k15 3848 1288 38 hirc lirc 3 20 422 814 1 8 28skdip /sop 28ssop 44qfp bs85c20-5 8mhz 12mhz 16mhz v lvr ~ 5.5v 8mhz ~ 16mhz 4k15 3848 1288 38 hirc lirc lxt 3 20 422 814 1 8 28skdip /sop 28ssop 44qfp
rev. 1.20 8 ????st 10? 2012 rev. 1.20 9 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver block diagram
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rev. 1.20 10 ???? st 10 ? 2012 rev. 1.20 11 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver

note: 1. bracketed pin names indicate non-default pinout remapping locations. 2. if the pin-shared pin functions have multiple outputs simultaneously , its pin names at the right side of the " / " sign can be used for higher priority.
rev. 1.20 10 ????st 10? 2012 rev. 1.20 11 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver pin description the function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. bs85b12-3 pin name function register select i/t o/t description p ? 0/sdi/sd ? p ? 0 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. sdi simc0 st spi data inp ? t sd ? simc0 st nmos i 2 c data i/o p ? 1/tck1/ int1/sseg10 p ? 1 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. tck1 tm1c0 st timer mod ? le 1 inp ? t int1 intc0 st external interr ? pt 1 inp ? t sseg10 slcdcn lcd software controlled lcd seg p ? 2/sck/scl p ? 2 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. sck simc0 st cmos spi serial clock scl simc0 st nmos i 2 c clock p ? 3/ scs p ? 3 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. scs simc0 st cmos spi slave select p ? 4/tck0/ int0/sseg11 p ? 4 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. tck0 tm0c0 st timer mod ? le 0 inp ? t int0 intc0 st external interr ? pt 0 inp ? t sseg11 slcdcn lcd software controlled lcd seg p ? 5/sseg12 p ? 5 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. sseg12 slcdcn lcd software controlled lcd seg p ? 6/sseg13 p ? 6 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. sseg13 slcdcn lcd software controlled lcd seg p ? 7/sdo p ? 7 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. sdo simc0 cmos spi data o ? tp ? t pb0/tp0_0/ scom0 pb0 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp0_0 tmpcn st cmos tm0 i/o scom0 slcdcn lcd software controlled lcd com pb1/tp0_1/ scom1 pb1 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp0_1 tmpcn st cmos tm0 i/o scom1 slcdcn lcd software controlled lcd com pb2/tp1b_0/ scom2 pb2 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp1b_0 tmpcn st cmos tm1 i/o scom2 slcdcn lcd software controlled lcd com pb3/tp1b_1/ scom3 pb3 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp1b_1 tmpcn st cmos tm1 i/o scom3 slcdcn lcd software controlled lcd com
rev. 1.20 12 ???? st 10 ? 2012 rev. 1.20 13 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver pin name function register select i/t o/t description pb4/tp1b_2/ pck/sseg8 pb4 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp1b_2 tmpcn st cmos tm1 i/o pck simc0 cmos peripheral clock o ? tp ? t sseg8 slcdcn lcd software controlled lcd seg pb5/pint/ tp1 ? /sseg9 pb5 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. pint mfi3 st peripheral interr ? pt inp ? t tp1 ? tmpcn st cmos tm1 i/o sseg9 slcdcn lcd software controlled lcd seg pc0/tp0_0/ sdo/sseg0/ key1 pc0 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp0_0 tmpcn st cmos tm0 i/o sdo simc0 cmos spi data o ? tp ? t sseg0 slcdcn lcd software controlled lcd seg key1 tkmnc1 ns to ? ch key inp ? t pc1/tp0_1/ sck/scl/ sseg1/key2 pc1 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp0_1 tmpcn st cmos tm0 i/o sck simc0 st cmos spi clock scl simc0 st nmos i 2 c clock sseg1 slcdcn lcd software controlled lcd seg key2 tkmnc1 ns to ? ch key inp ? t pc2/tp1b_0/ sdi/sd ? / sseg2/key3 pc2 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp1b_0 tmpcn st cmos tm1 i/o sdi simc0 st spi data inp ? t sd ? simc0 st nmos i 2 c data i/o sseg2 slcdcn lcd software controlled lcd seg key3 tkmnc1 ns to ? ch key inp ? t pc3/tp1b_1/ scs/sseg3/ key4 pc3 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp1b_1 tmpcn st cmos tm1 i/o scs simc0 st cmos spi slave select sseg3 slcdcn lcd software controlled lcd seg key4 tkmnc1 ns to ? ch key inp ? t pc4/tck0/ int0/tp1b_2/ sseg4/key5 pc4 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tck0 tm0c0 st timer mod ? le 0 inp ? t int0 intc0 st external interr ? pt 0 inp ? t tp1b_2 tmpcn st cmos tm1 i/o sseg4 slcdcn lcd software controlled lcd seg key5 tkmnc1 ns to ? ch key inp ? t pc5/tck1/ int1/tp1 ? / sseg5/key6 pc5 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tck1 tm1c0 st timer mod ? le 1 inp ? t int1 intc0 st external interr ? pt 1 inp ? t tp1 ? tmpcn st cmos tm1 i/o sseg5 slcdcn lcd software controlled lcd seg key6 tkmnc1 ns to ? ch key inp ? t pc6/pck/ sseg6/key7 pc6 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. pck simc0 cmos peripheral clock o ? tp ? t sseg6 slcdcn lcd software controlled lcd seg key7 tkmnc1 ns to ? ch key inp ? t
rev. 1.20 12 ????st 10? 2012 rev. 1.20 13 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver pin name function register select i/t o/t description pc7/pint/ sseg7/key8 pc7 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. pint mfi3 st peripheral interr ? pt inp ? t sseg7 slcdcn lcd software controlled lcd seg key8 tkmnc1 ns to ? ch key inp ? t key9 key9 ns to ? ch key inp ? t key10 key10 ns to ? ch key inp ? t key11 key11 ns to ? ch key inp ? t key12 key12 ns to ? ch key inp ? t vdd vdd pwr power s ? pply vss vss pwr gro ? nd note: i/t: input type o/t: output type register select: indicates register which selects alternative function pwr: power st: schmitt t rigger input cmos: cmos output nmos: nmos output lcd: lcd com or seg vbias output ns: non-standard input or output the pins in the table refect that of the package with the lar gest number of pins. for this reason not all pins may exist on all package types. bs85c20-3 pin name function register select i/t o/t description p ? 0/sdi/sd ? p ? 0 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. sdi simc0 st spi data inp ? t sd ? simc0 st nmos i 2 c data i/o p ? 1/tck1/ int1/sseg10 p ? 1 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. tck1 tm1c0 st timer mod ? le 1 inp ? t int1 intc0 st external interr ? pt 1 inp ? t sseg10 slcdcn lcd software controlled lcd seg p ? 2/sck/scl p ? 2 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. sck simc0 st cmos spi serial clock scl simc0 st nmos i 2 c clock p ? 3/ scs p ? 3 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. scs simc0 st cmos spi slave select p ? 4/tck0/ int0/sseg11 p ? 4 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. tck0 tm0c0 st timer mod ? le 0 inp ? t int0 intc0 st external interr ? pt 0 inp ? t sseg11 slcdcn lcd software controlled lcd seg
rev. 1.20 14 ???? st 10 ? 2012 rev. 1.20 15 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver pin name function register select i/t o/t description p ? 5/sseg12 p ? 5 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. sseg12 slcdcn lcd software controlled lcd seg p ? 6/sseg13 p ? 6 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. sseg13 slcdcn lcd software controlled lcd seg p ? 7/sdo p ? 7 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. sdo simc0 cmos spi data o ? tp ? t pb0/tp0_0/ scom0 pb0 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp0_0 tmpcn st cmos tm0 i/o scom0 slcdcn lcd software controlled lcd com pb1/tp0_1/ tp2_0/ scom1 pb1 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp0_1 tmpcn st cmos tm0 i/o tp2_0 tmpcn st cmos tm2 i/o scom1 slcdcn lcd software controlled lcd com pb2/tp1b_0/ tp2_1/ scom2 pb2 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp1b_0 tmpcn st cmos tm1 i/o tp2_1 tmpcn st cmos tm2 i/o scom2 slcdcn lcd software controlled lcd com pb3/tp1b_1/ scom3 pb3 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp1b_1 tmpcn st cmos tm1 i/o scom3 slcdcn lcd software controlled lcd com pb4/tp1b_2/ pck/sseg8 pb4 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp1b_2 tmpcn st cmos tm1 i/o pck simc0 cmos peripheral clock o ? tp ? t sseg8 slcdcn lcd software controlled lcd seg pb5/pint/ tp1 ? /sseg9 pb5 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. pint mfi3 st peripheral interr ? pt inp ? t tp1 ? tmpcn st cmos tm1 i/o sseg9 slcdcn lcd software controlled lcd seg pb6/sseg20 pb6 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. sseg20 slcdcn lcd software controlled lcd seg pb7/sseg21 pb7 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. sseg21 slcdcn lcd software controlled lcd seg pc0/tp0_0/ sdo/sseg0/ key1 pc0 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp0_0 tmpcn st cmos tm0 i/o sdo simc0 cmos spi data o ? tp ? t sseg0 slcdcn lcd software controlled lcd seg key1 tkmnc1 ns to ? ch key inp ? t pc1/tp0_1/ sck/scl/ sseg1/key2 pc1 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp0_1 tmpcn st cmos tm0 i/o sck simc0 st cmos spi clock scl simc0 st nmos i 2 c clock sseg1 slcdcn lcd software controlled lcd seg key2 tkmnc1 ns to ? ch key inp ? t
rev. 1.20 14 ????st 10? 2012 rev. 1.20 15 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver pin name function register select i/t o/t description pc2/tp1b_0/ sdi/sd ? / sseg2/key3 pc2 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp1b_0 tmpcn st cmos tm1 i/o sdi simc0 st spi data inp ? t sd ? simc0 st nmos i 2 c data i/o sseg2 slcdcn lcd software controlled lcd seg key3 tkmnc1 ns to ? ch key inp ? t pc3/tp1b_1/ scs/sseg3/ key4 pc3 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp1b_1 tmpcn st cmos tm1 i/o scs simc0 st cmos spi slave select sseg3 slcdcn lcd software controlled lcd seg key4 tkmnc1 ns to ? ch key inp ? t pc4/tck0/ int0/tp1b_2/ sseg4/key5 pc4 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tck0 tm0c0 st timer mod ? le 0 inp ? t int0 intc0 st external interr ? pt 0 inp ? t tp1b_2 tmpcn st cmos tm1 i/o sseg4 slcdcn lcd software controlled lcd seg key5 tkmnc1 ns to ? ch key inp ? t pc5/tck1/ int1/tp1 ? / sseg5/key6 pc5 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tck1 tm1c0 st timer mod ? le 1 inp ? t int1 intc0 st external interr ? pt 1 inp ? t tp1 ? tmpcn st cmos tm1 i/o sseg5 slcdcn lcd software controlled lcd seg key6 tkmnc1 ns to ? ch key inp ? t pc6/tck2/ pck/sseg6/ key7 pc6 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tck2 tm2c0 st timer mod ? le 2 inp ? t pck simc0 cmos peripheral clock o ? tp ? t sseg6 slcdcn lcd software controlled lcd seg key7 tkmnc1 ns to ? ch key inp ? t pc7/pint/ sseg7/key8 pc7 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. pint mfi3 st peripheral interr ? pt inp ? t sseg7 slcdcn lcd software controlled lcd seg key8 tkmnc1 ns to ? ch key inp ? t pd0/tck2/ key13 pd0 pdpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tck2 tm2c0 st timer mod ? le 2 inp ? t key13 tkmnc1 ns to ? ch key inp ? t pd1/key14 pd1 pdpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. key14 tkmnc1 ns to ? ch key inp ? t pd2/key15 pd2 pdpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. key15 tkmnc1 ns to ? ch key inp ? t pd3/key16 pd3 pdpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. key16 tkmnc1 ns to ? ch key inp ? t pd4/key17 pd4 pdpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. key17 tkmnc1 ns to ? ch key inp ? t pd5/key18 pd5 pdpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. key18 tkmnc1 ns to ? ch key inp ? t pd6/key19 pd6 pdpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. key19 tkmnc1 ns to ? ch key inp ? t
rev. 1.20 16 ???? st 10 ? 2012 rev. 1.20 17 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver pin name function register select i/t o/t description pd7/key20 pd7 pdpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. key20 tkmnc1 ns to ? ch key inp ? t pe0/pint/ sseg14 pe0 pepu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. pint mfi3 st peripheral interr ? pt inp ? t sseg14 slcdcn lcd software controlled lcd seg pe1/tp2_0/ pck/sseg15 pe1 pepu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp2_0 tmpcn st cmos tm2 i/o pck simc0 cmos peripheral clock o ? tp ? t sseg15 slcdcn lcd software controlled lcd seg pe2/tp2_1/ scs/sseg16 pe2 pepu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp2_1 tmpcn st cmos tm2 i/o scs simc0 st cmos spi select sseg16 slcdcn lcd software controlled lcd seg pe3/sck/ scl/sseg17 pe3 pepu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. sck simc0 st cmos spi serial clock scl simc0 st nmos i 2 c clock sseg17 slcdcn lcd software controlled lcd seg pe4/sdi/ sd ? /sseg18 pe4 pepu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. sdi simc0 st spi data inp ? t sd ? simc0 st nmos i 2 c data i/o sseg18 slcdcn lcd software controlled lcd seg pe5/sdo/ sseg19 pe5 pepu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. sdo simc0 st cmos spi data o ? tp ? t sseg19 slcdcn lcd software controlled lcd seg key9 key9 ns to ? ch key inp ? t key10 key10 ns to ? ch key inp ? t key11 key11 ns to ? ch key inp ? t key12 key12 ns to ? ch key inp ? t vdd vdd pwr power s ? pply vss vss pwr gro ? nd note: i/t: input type o/t: output type register select: indicates register which selects alternative function pwr: power st: schmitt t rigger input cmos: cmos output nmos: nmos output lcd: lcd com or seg vbias output ns: non-standard input or output the pins in the table refect that of the package with the lar gest number of pins. for this reason not all pins may exist on all package types.
rev. 1.20 16 ????st 10? 2012 rev. 1.20 17 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85c20-5 pin name function register select i/t o/t description p ? 0/sdi/sd ? p ? 0 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. sdi simc0 st spi data inp ? t sd ? simc0 st nmos i 2 c data i/o p ? 1/tck1/ int1/sseg10 p ? 1 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. tck1 tm1c0 st timer mod ? le 1 inp ? t int1 intc0 st external interr ? pt 1 inp ? t sseg10 slcdcn lcd software controlled lcd seg p ? 2/sck/scl p ? 2 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. sck simc0 st cmos spi serial clock scl simc0 st nmos i 2 c clock p ? 3/ scs p ? 3 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. scs simc0 st cmos spi slave select p ? 4/tck0/ int0/sseg11 p ? 4 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. tck0 tm0c0 st timer mod ? le 0 inp ? t int0 intc0 st external interr ? pt 0 inp ? t sseg11 slcdcn lcd software controlled lcd seg osc2 osc2 osc lxt oscillator pin osc1 osc1 osc lxt oscillator pin p ? 7/sdo p ? 7 p ? w u p ? pu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p and wake- ? p. sdo simc0 cmos spi data o ? tp ? t pb0/tp0_0/ scom0 pb0 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp0_0 tmpcn st cmos tm0 i/o scom0 slcdcn lcd software controlled lcd com pb1/tp0_1/ tp2_0/ scom1 pb1 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp0_1 tmpcn st cmos tm0 i/o tp2_0 tmpcn st cmos tm2 i/o scom1 slcdcn lcd software controlled lcd com pb2/tp1b_0/ tp2_1/ scom2 pb2 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp1b_0 tmpcn st cmos tm1 i/o tp2_1 tmpcn st cmos tm2 i/o scom2 slcdcn lcd software controlled lcd com pb3/tp1b_1/ scom3 pb3 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp1b_1 tmpcn st cmos tm1 i/o scom3 slcdcn lcd software controlled lcd com pb4/tp1b_2/ pck/sseg8 pb4 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp1b_2 tmpcn st cmos tm1 i/o pck simc0 cmos peripheral clock o ? tp ? t sseg8 slcdcn lcd software controlled lcd seg
rev. 1.20 18 ???? st 10 ? 2012 rev. 1.20 19 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver pin name function register select i/t o/t description pb5/pint/ tp1 ? /sseg9 pb5 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. pint mfi3 st peripheral interr ? pt inp ? t tp1 ? tmpcn st cmos tm1 i/o sseg9 slcdcn lcd software controlled lcd seg pb6/sseg20 pb6 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. sseg20 slcdcn lcd software controlled lcd seg pb7/sseg21 pb7 pbpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. sseg21 slcdcn lcd software controlled lcd seg pc0/tp0_0/ sdo/sseg0/ key1 pc0 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp0_0 tmpcn st cmos tm0 i/o sdo simc0 cmos spi data o ? tp ? t sseg0 slcdcn lcd software controlled lcd seg key1 tkmnc1 ns to ? ch key inp ? t pc1/tp0_1/ sck/scl/ sseg1/key2 pc1 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp0_1 tmpcn st cmos tm0 i/o sck simc0 st cmos spi clock scl simc0 st nmos i 2 c clock sseg1 slcdcn lcd software controlled lcd seg key2 tkmnc1 ns to ? ch key inp ? t pc2/tp1b_0/ sdi/sd ? / sseg2/key3 pc2 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp1b_0 tmpcn st cmos tm1 i/o sdi simc0 st spi data inp ? t sd ? simc0 st nmos i 2c data i/o sseg2 slcdcn lcd software controlled lcd seg key3 tkmnc1 ns to ? ch key inp ? t pc3/tp1b_1/ scs/sseg3/ key4 pc3 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp1b_1 tmpcn st cmos tm1 i/o scs simc0 st cmos spi slave select sseg3 slcdcn lcd software controlled lcd seg key4 tkmnc1 ns to ? ch key inp ? t pc4/tck0/ int0/tp1b_2/ sseg4/key5 pc4 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tck0 tm0c0 st timer mod ? le 0 inp ? t int0 intc0 st external interr ? pt 0 inp ? t tp1b_2 tmpcn st cmos tm1 i/o sseg4 slcdcn lcd software controlled lcd seg key5 tkmnc1 ns to ? ch key inp ? t pc5/tck1/ int1/tp1 ? / sseg5/key6 pc5 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tck1 tm1c0 st timer mod ? le 1 inp ? t int1 intc0 st external interr ? pt 1 inp ? t tp1 ? tmpcn st cmos tm1 i/o sseg5 slcdcn lcd software controlled lcd seg key6 tkmnc1 ns to ? ch key inp ? t pc6/tck2/ pck/sseg6/ key7 pc6 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tck2 tm2c0 st timer mod ? le 2 inp ? t pck simc0 cmos peripheral clock o ? tp ? t sseg6 slcdcn lcd software controlled lcd seg key7 tkmnc1 ns to ? ch key inp ? t
rev. 1.20 18 ????st 10? 2012 rev. 1.20 19 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver pin name function register select i/t o/t description pc7/pint/ sseg7/key8 pc7 pcpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. pint mfi3 st peripheral interr ? pt inp ? t sseg7 slcdcn lcd software controlled lcd seg key8 tkmnc1 ns to ? ch key inp ? t pd0/tck2/ key13 pd0 pdpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tck2 tm2c0 st timer mod ? le 2 inp ? t key13 tkmnc1 ns to ? ch key inp ? t pd1/key14 pd1 pdpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. key14 tkmnc1 ns to ? ch key inp ? t pd2/key15 pd2 pdpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. key15 tkmnc1 ns to ? ch key inp ? t pd3/key16 pd3 pdpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. key16 tkmnc1 ns to ? ch key inp ? t pd4/key17 pd4 pdpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. key17 tkmnc1 ns to ? ch key inp ? t pd5/key18 pd5 pdpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. key18 tkmnc1 ns to ? ch key inp ? t pd6/key19 pd6 pdpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. key19 tkmnc1 ns to ? ch key inp ? t pd7/key20 pd7 pdpu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. key20 tkmnc1 ns to ? ch key inp ? t pe0/pint/ sseg14 pe0 pepu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. pint mfi3 st peripheral interr ? pt inp ? t sseg14 slcdcn lcd software controlled lcd seg pe1/tp2_0/ pck/sseg15 pe1 pepu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp2_0 tmpcn st cmos tm2 i/o pck simc0 cmos peripheral clock o ? tp ? t sseg15 slcdcn lcd software controlled lcd seg pe2/tp2_1/ scs/sseg16 pe2 pepu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. tp2_1 tmpcn st cmos tm2 i/o scs simc0 st cmos spi select sseg16 slcdcn lcd software controlled lcd seg pe3/sck/ scl/sseg17 pe3 pepu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. sck simc0 st cmos spi serial clock scl simc0 st nmos i 2 c clock sseg17 slcdcn lcd software controlled lcd seg pe4/sdi/ sd ? /sseg18 pe4 pepu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. sdi simc0 st spi data inp ? t sd ? simc0 st nmos i 2 c data i/o sseg18 slcdcn lcd software controlled lcd seg pe5/sdo/ sseg19 pe5 pepu st cmos general p ? rpose i/o. re ? ister enabled p ? ll- ? p. sdo simc0 st cmos spi data o ? tp ? t sseg19 slcdcn lcd software controlled lcd seg key9 key9 ns to ? ch key inp ? t key10 key10 ns to ? ch key inp ? t key11 key11 ns to ? ch key inp ? t key12 key12 ns to ? ch key inp ? t
rev. 1.20 20 ???? st 10 ? 2012 rev. 1.20 21 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver pin name function register select i/t o/t description vdd vdd pwr power s ? pply vss vss pwr gro ? nd note: i/t: input type o/t: output type register select: indicates register which selects alternative function pwr: power st: schmitt t rigger input cmos: cmos output nmos: nmos output lcd: lcd com or seg vbias output ns: non-standard input or output the pins in the table refect that of the package with the lar gest number of pins. for this reason not all pins may exist on all package types. absolute maximum ratings supply v oltage .............. .................................................................................. v ss ?0.3v to v ss +6.0v input v oltage .............. .................................................................................... v ss ? 0.3v to v dd +0.3v storage t emperature ............... ..................................................................................... -50? c to 125?c operating t emperature .............. .................................................................................... -40? c to 85 ?c i oh t otal .............. .................................................................................................................... -100ma i ol t otal .............. ..................................................................................................................... 100ma total power dissipation .............. .......................................................................................... 500mw note: t hese a re st ress ra tings onl y. st resses e xceeding t he ra nge spe cified und er "absol ute ma ximum ratings" m ay c ause su bstantial d amage t o t hese d evices. fu nctional o peration o f t hese d evices a t other c onditions be yond t hose l isted i n t he spe cifcation i s no t i mplied a nd pr olonged e xposure t o extreme conditions may affect devices reliability.
rev. 1.20 20 ????st 10? 2012 rev. 1.20 21 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver d.c. characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operatin ? volta ? e (hirc) f sys =8mhz v lvr 5.5 v f sys =12mhz 2.7 5.5 v f sys =16mhz 4.5 5.5 v i dd1 operatin ? c ? rrent (hirc) ? (f sys =f h) 3v no load ? f h =8mhz ? wdt enable 1.2 1.8 m ? 5v 2.7 4.1 m ? 3v no load ? f h =12mhz ? wdt enable 1.9 2.9 m ? 5v 4.2 6.3 m ? 5v no load ? f h =16mhz ? wdt enable 5.6 8.4 m ? i dd2 operatin ? c ? rrent (lirc) ? (f sys =f l ) 3v no load ? f l =32khz ? wdt enable 15 30 ? 5v 30 50 ? i idle01 idle0 mode standby c ? rrent (lxt on) 3v no load ? wdt enable ? lxtlp=0 5 10 ? 5v 18 30 ? 3v no load ? wdt enable ? lxtlp=1 2.5 5.0 ? 5v 6 10 ? i idle02 idle0 mode standby c ? rrent (lirc on) 3v no load ? lvr disable 1.5 3.0 ? 5v 3.0 6.0 ? i idle03 idle0 mode standby c ? rrent (lxt and lirc on) 3v no load ? wdt enable ? lxtlp=0 6.5 13 ? 5v 13 26 ? 3v no load ? wdt enable ? lxtlp=1 6 12 ? 5v 12 24 ? i idle1 idle1 mode standby c ? rrent 3v no load ? lvr disable ? f sys =12mhz on 0.9 1.4 m ? 5v 1.6 2.4 m ? i sleep sleep1 mode standby c ? rrent 3v no load ? lvr disable 1.5 3.0 ? 5v 2.5 5.0 ? v il inp ? t low volta ? e for i/o ports or inp ? t pins 5v 0 1.5 v 0 0.2v dd v v ih inp ? t hi ? h volta ? e for i/o ports or inp ? t pins 5v 3.5 5.0 v 0.8v dd v dd v v ol1 o ? tp ? t low volta ? e i/o port 3v i ol =9m ? 0.3 v 5v i ol =20m ? 0.5 v v ol2 o ? tp ? t low volta ? e i/o port (pb) (hi ? h c ? rrent enable) 3v i ol =18m ? 0.3 v 5v i ol =40m ? 0.5 v v oh1 o ? tp ? t hi ? h volta ? e i/o port 3v i oh =-3.2m ? 2.7 v 5v i oh =-7.4m ? 4.5 v v oh2 o ? tp ? t hi ? h volta ? e i/o port (p ?? pe) (hi ? h c ? rrent enable) 3v i oh =-6.4m ? 2.7 v 5v i oh =-15.0m ? 4.5 v v lvr lvr volta ? e level lvr enable -5% 2.55 +5% v v lvd lvd volta ? e level lvden=1 ? v lvd =2.7v -5% 2.70 +5% v lvden=1 ? v lvd =3.0v -5% 3.00 +5% v lvden=1 ? v lvd =3.3v -5% 3.30 +5% v lvden=1 ? v lvd =3.6v -5% 3.60 +5% v lvden=1 ? v lvd =4.2v -5% 4.20 +5% v i lvd ? dditional power cons ? mption if lvd is used norm ? l or slow mode 2 5 ? idle or sleep mode 15 30 ?
rev. 1.20 22 ???? st 10 ? 2012 rev. 1.20 23 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver symbol parameter test conditions min. typ. max. unit v dd conditions i scom scom operatin ? c ? rrent 5v isel[1:0]=00 17.5 25.0 32.5 ? isel[1:0]=01 35 50 65 ? isel[1:0]=10 70 100 130 ? isel[1:0]=11 140 200 260 ? i sseg sseg operatin ? c ? rrent 5v isel[1:0]=00 17.5 25.0 32.5 ? isel[1:0]=01 35 50 65 ? isel[1:0]=10 70 100 130 ? isel[1:0]=11 140 200 260 ? v ssom volta ? e for lcd scom 5v 1/3 v dd -3% 0.33 +3% v dd 2/3 v dd -3% 0.67 +3% v dd v sseg volta ? e for lcd sseg 5v 1/3 v dd -3% 0.33 +3% v dd 2/3 v dd -3% 0.67 +3% v dd r ph p ? ll-hi ? h resistance for i/o ports 3v 20 60 100 k 5v 10 30 50 k a.c. characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions f cpu operatin ? clock v lvr ~5.5v dc 8 mhz 2.7v~5.5v dc 12 mhz 4.5v~5.5v dc 16 mhz f hirc system clock (hirc) 3v/5v ta=25?c -2% 8 +2% mhz 3v/5v ta=25?c -2% 12 +2% mhz 5v ta=25?c -2% 16 +2% mhz 3v/5v ta=0~70?c -4% 8 +3% mhz 3v/5v ta=0~70?c -4% 12 +3% mhz 5v ta=0~70?c -4% 16 +3% mhz 2.5v~ 4.0v ta=0~70?c -9% 8 +6% mhz 3.0v~ 5.5v ta=0~70?c -5% 8 +12% mhz 2.7v~ 4.0v ta=0~70?c -9% 12 +5% mhz 3.0v~ 5.5v ta=0~70?c -5% 12 +11% mhz 4.5v~ 5.5v ta=0~70?c -5% 16 +5% mhz 2.5v~ 4.0v ta=-40?c~85?c -12% 8 +6% mhz 3.0v~ 5.5v ta=-40?c~85?c -8% 8 +12% mhz 2.7v~ 4.0v ta=-40?c~85?c -13% 12 +5% mhz 3.0v~ 5.5v ta=-40?c~85?c -8% 12 +11% mhz 4.5v~ 5.5v ta=-40?c~85?c -7% 16 +5% mhz
rev. 1.20 22 ????st 10? 2012 rev. 1.20 23 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver symbol parameter test conditions min. typ. max. unit v dd conditions f lirc system clock (lirc) 5v -10% 32 +10% khz 2.2v~ 5.5v ta=-40?c~85?c -50% 32 +60% khz f timer timer inp ? t pin freq ? ency 1 f sys t int interr ? pt p ? lse width 1 s t lvr low volta ? e width to reset 60 120 240 s t lvd low volta ? e width to interr ? pt 180 240 360 s t lvds lvdo stable time 15 s t eerd eeprom read time 2 4 t sys t eewr eeprom write time 2 4 ms t sst system start- ? p timer period (wake- ? p from h ? lt) f sys =hirc 15~16 t sys f sys =lirc 1~2 note: 1. t sys =1/f sys 2. to maintain the acc ? racy of the internal hirc oscillator freq ? ency ? a 0.1f deco ? plin ? capacitor sho ? ld be connected between vdd and vss and located as close to the device as possible. power-on reset characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions v por vdd start volta ? e to ens ? re power-on reset 100 mv r por ? c vdd raisin ? rate to ens ? re power-on reset 0.035 v/ms t por minim ? m time for vdd stays at v por to ens ? re power-on reset 1 ms
rev. 1.20 24 ???? st 10 ? 2012 rev. 1.20 25 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver oscillator temperature/frequency characteristics the following characteristic graphics depicts typical oscillator behavior . the data presented here is a statistic al summary of data gathered on units from dif ferent lots over a period of time. this is for information only and the fgures were not tested during manufacturing. in some of the graphs, the data exceeding the specifed operating range are shown for information purposes only. the device will operate properly only within the specifed range. internal rc -- 8mhz (3v) 7.300 7.400 7.500 7.600 7.700 7.800 7.900 8.000 8.100 8.200 8.300 -60 -40 -20 0 20 40 60 80 100 120 140 ta(c) f sys (mhz) 2.5v 2.7v 3.0v 4.0v internal rc -- 8mhz (5v) 7.400 7.600 7.800 8.000 8.200 8.400 8.600 8.800 -60 -40 -20 0 20 40 60 80 100 120 140 ta(c) f sys (mhz) 3.0v 4.0v 4.5v 4.75v 5.0v 5.25v 5.5v
rev. 1.20 24 ????st 10? 2012 rev. 1.20 25 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver internal rc -- 12mhz (3v) 10.800 11.000 11.200 11.400 11.600 11.800 12.000 12.200 12.400 -60 -40 -20 0 20 40 60 80 100 120 140 ta(c) f sys (mhz) 2.7v 3.0v 4.0v internal rc -- 12mhz (5v) 11.400 11.600 11.800 12.000 12.200 12.400 12.600 12.800 13.000 -60 -40 -20 0 20 40 60 80 100 120 140 ta(c) f sys (mhz) 3.0v 4.0v 4.5v 4.75v 5.0v 5.25v 5.5v
rev. 1.20 26 ???? st 10 ? 2012 rev. 1.20 27 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver system architecture a key factor in the high-performanc e features of the holtek range of microcontroller is attributed to their internal system architecture. the range of devices take advantage of the usual features found within risc microcontroller providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or c all i nstructions. an 8-bi t wi de al u i s use d i n pra ctically a ll i nstruction se t ope rations, whi ch carries out arithme tic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the d ata m emory and can be directly or indirectly addressed. the simpl e addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o control system with maximum relia bility and fexibility . this makes the device suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a high or low speed oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. internal rc -- 16mhz (5v) 15.300 15.400 15.500 15.600 15.700 15.800 15.900 16.000 16.100 16.200 16.300 16.400 -60 -40 -20 0 20 40 60 80 100 120 140 ta(c) f sys (mhz) 4.5v 4.75v 5.0v 5.25v 5.5v
rev. 1.20 26 ????st 10? 2012 rev. 1.20 27 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver
? ? ? ? ? ? ? ? system clocking and pipelining
? ? ? ? ? ? ? ? ? ? instruction fetching for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into accou nt by programmers in timing sensitive applications. program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as "jmp" or "call" that demand a jump to a non-consecutive program memory address. only the lower 8 bits, known as the program counter low register , are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly, h owever, a s o nly t his l ow b yte is available for manipulation, the jumps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.20 28 ???? st 10 ? 2012 rev. 1.20 29 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver stack this is a special part of the memory which is used to save the contents of the program counter only . the stack has multiple levels depending upon the device and is neither part of the data nor part of the p rogram sp ace, a nd i s n either r eadable n or wr iteable. t he a ctivated l evel i s i ndexed b y t he st ack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allo wing the programmer to use the struct ure more easily . however , when the stack is full, a call subroutine instruction can still be execu ted which will result in a stack overfow . precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost. device stack levels bs85b12-3 4 bs85c20-3 /bs85c20-5 8
arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.20 28 ????st 10? 2012 rev. 1.20 29 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver flash program memory the program memory is the location where the user code or program is stored. for this device series the program memory is flash type, which means it can be programmed and re-programmed a l arge num ber of t imes, a llowing t he use r t he c onvenience of c ode m odification on t he sa me device. by using the appropriate programming tools, these flash device s of fer users the fexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. structure the program memory has a capacity of 2k 15 bits or 4k 15 bits. the program memory is addressed by the program counter and also contains data, table informati on and interrupt entries. table data, which can be setup in any location within the program memory , is addressed by a separate table pointer register. device capacity bs85b12-3 2k 15 bs85c20-3 /bs85c20-5 4k 15

special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the "t abrd[m]" or "t abrdl[m]" instructions, respectively . when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data me mory r egister [ m] a s sp ecified i n t he i nstruction. t he h igher o rder t able d ata b yte f rom the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as "0". the accompanying diagram illustrates the addressing data fow of the look-up table.
rev. 1.20 30 ???? st 10 ? 2012 rev. 1.20 31 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver

table program example the following example using the bs85b12-3 shows how the table pointer and table data is defned and retrieved from the microcontroller . this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is "700h" which refers to the start address of the last page within the 2k words program memory of the device. the table pointer is setup here to have an initial value of "06h". this will ensure that the frst data read from t he da ta t able wi ll be a t t he progra m me mory a ddress "706h" or 6 l ocations a fter t he start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the "t abrd [m]" instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the "tabrd [m]" instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address mov tblp,a ; is referenced mov a,07h ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at ; program memory address "706h" transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at ; program memory address "705h" transferred to tempreg2 and tblh in ; this example the data "1ah" is transferred to tempreg1 and data ; "0fh" to register tempreg2 : : org 700h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
rev. 1.20 30 ????st 10? 2012 rev. 1.20 31 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver in circuit programming the p rovision o f fl ash t ype pr ogram me mory p rovides t he u ser wi th a m eans o f c onvenient a nd easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in- circuit using a 5-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming o r u pgrading t he p rogram a t a l ater st age. t his enables product m anufacturers to e asily keep thei r manufa ctured products supplied with the latest program releases without removal and re- insertion of the device. the holtek flash mcu to w riter programming pin correspondence table is as follows: holtek writer device pin description pin name pin name sd ? t ? p ? 0 serial ? ddress and data -- read/write sclk p ? 2 ? ddress and data serial clock inp ? t vpp p ? 7 reset inp ? t vdd vdd power s ? pply (5.0v) vss vss gro ? nd the program memory and eeprom data memory can both be programmed serially in-circuit using this 5-wi re inte rface. dat a is downloaded and upl oaded serial ly on a single pin wit h an additi onal line for the clock. t wo additional lines are required for the power supply and one line for the reset. the t echnical d etails r egarding t he i n-circuit p rogramming o f t he d evices a re b eyond t he sc ope o f this document and will be supplied in supplementary literature. during the programming process the p a7 pin will be held low by the programmer disabling the normal operation of the microcontroller and taking control of the p a0 and p a2 i/o pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins.
note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf.
rev. 1.20 32 ???? st 10 ? 2012 rev. 1.20 33 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. he re a re l ocated r egisters wh ich a re n ecessary f or c orrect o peration o f t he d evice. ma ny of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. device capacity bank 0 bank 1 bank 2 bs85b12-3 2568 80h~ffh 80h~ffh bs85c20-3 /bs85c20-5 3848 80h~ffh 80h~ffh 80h~ffh general purpose data memory the second area of data memory is known as the general purpose data memory , which is reserved for general purpose use. all locatio ns within this area are read and write accessible under program control. the overall data memory is subdivided into two or three banks. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is onl y a ccessible i n ba nk 1. swi tching be tween t he di fferent da ta me mory ba nks i s a chieved by setting the bank pointer to the correct value. the start address of the data memory for all devices is the address 00h. special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of "00h" and writing to the registers indirectly will result in no operation.
rev. 1.20 32 ????st 10? 2012 rev. 1.20 33 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver memory pointers C mp0, mp1 two me mory po inters, k nown a s mp0 a nd mp1 a re p rovided. t hese me mory po inters a re physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the releva nt indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specifed by the related memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according to bp register . direct addressing can only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. note that for this series of devices, the memory pointers, mp0 and mp1, are both 8-bit registers and used to access the data memory together with their corresponding indirect addressing registers iar0 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org 0 0h start: m ov a,04h ; setup size of block m ov block,a mov a ,offset ad res1 ; a ccumulator l oaded w ith f rst r am ad dress mov m p0,a ; s etup m emory po inter wi th f rst r am a ddress loop: clr i ar0 ; c lear t he d ata a t ad dress d efned b y m p0 i nc mp0 ; increment memory pointer s dz block ; check if last memory location has been cleared jm p loop continue: the important point to note here is that in the example shown above, no reference is made to specifc ram addresses.
rev. 1.20 34 ???? st 10 ? 2012 rev. 1.20 35 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver

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rev. 1.20 34 ????st 10? 2012 rev. 1.20 35 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver general purpose data memory bank pointer C bp for this series of devices, the data memory is divided into two or three banks. selecting the required data memory area is achieved using the bank pointer . bit 0 and 1 is used to select data memory banks 0~2. the data memory is initialised to bank 0 after a reset, except for a wd t time-out reset in the power down mode, in which case, the data memory bank remains unaf fected. it should be noted that the special function data memory is not af fected by the bank selection, which means that the special function regi sters ca n be ac cessed from wi thin any bank. di rectly addre ssing the da ta me mory will always result in bank 0 being accessed irrespective of the value of the bank pointer . accessing data from banks other than bank 0 must be implemented using indirect addressing. bp register C bs85b12-3 bit 7 6 5 4 3 2 1 0 name dmbp0 r/w r/w por 0 bit 7~1 unimplemented, read as "0" bit 0 dmbp0 : select data memory banks 0: bank 0 1: bank 1 bp register C bs85c20-3/bs85c20-5 bit 7 6 5 4 3 2 1 0 name dmbp1 dmbp0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 dmbp1, dmbp0 : select data memory banks 00: bank 0 01: bank 1 10: bank 2 11: undefned
rev. 1.20 36 ???? st 10 ? 2012 rev. 1.20 37 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user defi ned regi ster and anot her, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nter a nd i ndicates t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the "inc" or "dec" instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the "clr wdt" or "hal t" instruction. the pdf fag is af fected only by executing the "halt" or "clr wdt" instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared.
rev. 1.20 36 ????st 10? 2012 rev. 1.20 37 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver ? pdf is cleared by a system power-up or executing the "clr wdt" instruction. pdf is set by executing the "halt" instruction. ? to is cleared by a system power-up or executing the "clr wdt" or "halt" instruction. t o is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ? c c r/w r r r/w r/w r/w r/w por 0 0 x x x x "x" ? nknown bit 7~6 unimplemented, read as "0" bit 5 to : watchdog time-out fag 0: after power up or executing the "clr wdt"or "halt" instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.20 38 ???? st 10 ? 2012 rev. 1.20 39 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver eeprom data memory the devices contain an area of internal eeprom data memory . eeprom, which stands for electrically e rasable progra mmable re ad onl y me mory, i s by i ts na ture a non-vol atile form of re-programmable memory , with data retention even when its power supply is removed. by incorporating this kind of data memory , a w hole new hos t of application pos sibilities are made available to the designer . the avail ability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is 64 8 or 128 8 bits for this series of devices. unlike the program memory and ram data memory , the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. read and w rite operations to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. device capacity address bs85b12-3 648 00h ~ 3fh bs85c20-3 /bs85c20-5 1288 00h ~ 7fh eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address register , eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same was as any other special function register . the eec register however , being located in bank1, cannot be addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register , iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register , bp, set to the value, 01h, before any operations on the eec register are executed. eeprom register list ? bs85b12-3 name bit 7 6 5 4 3 2 1 0 ee ? d5 d4 d3 d2 d1 d0 eed d7 d6 d5 d4 d3 d2 d1 d0 eec wren wr rden rd ? bs85c20-3/bs85c20-5 name bit 7 6 5 4 3 2 1 0 ee ? d6 d5 d4 d3 d2 d1 d0 eed d7 d6 d5 d4 d3 d2 d1 d0 eec wren wr rden rd
rev. 1.20 38 ????st 10? 2012 rev. 1.20 39 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver eea register ? bs85b12-3 bit 7 6 5 4 3 2 1 0 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por x x x x x x "x" ? nknown bit 7~6 unimplemented, read as "0" bit 5~0 data eeprom address data eeprom address bit 5~bit 0 ? bs85c20-3/bs85c20-5 bit 7 6 5 4 3 2 1 0 name d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x "x" ? nknown bit 7 unimplemented, read as "0" bit 6~0 data eeprom address data eeprom address bit 6~bit 0 eec register bit 7 6 5 4 3 2 1 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as "0" bit 3 wren : data eeprom write enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom write control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero w ill inhibit d ata eeprom read operations.
rev. 1.20 40 ???? st 10 ? 2012 rev. 1.20 41 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set hi gh by the applicat ion program will activ ate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to "1" at the same time in one instruction. the wr and rd can not be set to "1" at the same time. eed register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" ? nknown bit 7~0 data eeprom data data eeprom data bit 7~bit 0 reading data from the eeprom to read data from the eeprom, the read enable bit, rden, in the eec register must frst be set high to enable the read function. the eep rom addres s of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle terminates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation is executed. the application program can poll the rd bit to determine when the data is valid for reading. writing data to the eeprom the eeprom address of the data to be written must frst be placed in the eea register and the data placed in the eed register . t o write data to the eeprom, the write enable bit, wren, in the eec register must frst be set high to enable the write function. after this, the wr bit in the eec register must be immediately set high to initiate a write cycle. these two instructions must be executed consecutively. t he global interrupt bit emi should also frst be cleared before implementing any write operations, and then set again after the write cycle has started. note that setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using a n i nternal t imer wh ose o peration i s a synchronous t o m icrocontroller sy stem c lock, a c ertain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered- on t he w rite ena ble bit i n t he control regist er wi ll be cl eared pre venting any writ e opera tions. al so at power -on the bank pointer , bp , will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the w rite enable bit in the control register is cleared will safeguard against incorrect write operations.
rev. 1.20 40 ????st 10? 2012 rev. 1.20 41 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register . however as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must als o be set. when an eeprom w rite cycle ends, the d ef reques t flag and its associated multi-function interrupt request fag will both be set. if the global, eeprom and multi- function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt fag will be automatically reset, the eeprom interrupt fag must be manually reset by the application program. more details can be obtained in the interrupt section. programming considerations care mus t be taken that data is not inadvertently w ritten to the eepro m. protection can be enhanced by ensuring that the w rite enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. al though certainly not necessary, c onsideration might be given i n the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. programming examples reading data from the eeprom C polling method mov a , ee prom_adres ; u ser d efned ad dress mov e ea, a mov a , 0 40h ; se tup m emory p ointer m p1 mov mp1, a ; mp1 p oints t o e ec r egister mov a , 0 1h ; se tup b ank p ointer mov b p, a set i ar1.1 ; s et r den b it, e nable r ead o perations set i ar1.0 ; s tart r ead c ycle - s et r d b it back: sz i ar1.0 ; c heck f or re ad c ycle e nd jmp b ack clr i ar1 ; d isable ee prom re ad/write clr bp mov a , ee d ; m ove re ad d ata t o re gister mov r ead_data, a writing data to the eeprom C polling method clr e mi mov a , ee prom_adres ; u ser d efned ad dress mov e ea, a mov a , e eprom_data ; u ser d efned da ta mov e ed, a mov a , 0 40h ; se tup m emory p ointer m p1 mov mp1, a ; mp1 p oints t o e ec r egister mov a , 0 1h ; se tup b ank p ointer mov b p, a set i ar1.3 ; s et w ren b it, e nable w rite o perations set i ar1.2 ; start w rite c ycle-set w r b it-executed i mmediately a fter s et w ren b it set e mi back: sz i ar1.2 ; c heck f or wr ite c ycle e nd jmp b ack clr i ar1 ; d isable ee prom re ad/write clr bp
rev. 1.20 42 ???? st 10 ? 2012 rev. 1.20 43 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver oscillator various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and registers. oscillator overview in addition to being the source of the main system clock the slow speed oscillators also provide clock sources for the w atchdog t imer and t ime base. external oscilla tors requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided t o fo rm a wi de ra nge of bo th fa st a nd sl ow syst em osc illators. al l osc illator op tions a re selected through registers. the higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. w ith the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. device type name freq. pins ? ll internal hi ? h speed hirc 8,12 or 16mhz internal low speed lirc 32khz bs85c20-5 external low speed lxt 32.768khz osc1/osc2 oscillator types system clock confgurations there are two methods of generating the system clock, a high speed internal clock source and low speed internal clock source. the high speed oscillator is an internal 8mhz, 12mhz or 16mhz rc oscillator w hile the low s peed os cillator is an internal 32kh z rc os cillator. both os cillators are fully i ntegrated a nd d o n ot r equire e xternal c omponents. se lecting wh ether t he l ow o r h igh sp eed oscillator i s use d a s t he syst em osc illator i s i mplemented usi ng t he hl clk bi t a nd cks2 ~ cks0 bits in the smod register allowing the system clock to be dynamically selected. internal high speed rc oscillator C hirc the internal h igh speed rc os cillator is a fully integrated s ystem os cillator requiring no external components. the internal rc oscillator has a power on default frequency of 8 mhz but can be selected t o be e ither 8mhz , 12mhz or 16mhz usi ng t he hircs1 a nd hircs0 bi ts i n t he ct rl register. device trimming during the manufacturing process and the inclusion of internal frequency compensation circ uits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised.
rev. 1.20 42 ????st 10? 2012 rev. 1.20 43 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver ctrl register bit 7 6 5 4 3 2 1 0 name hircs1 hircs0 d1 d0 r/w r/w r/w r/w r/w por 0 0 0 0 "x" ? nknown bit 7~6 unimplemented, read as "0" bit 5~4 hircs1, hircs0 : high frequency clock select 00: 8mhz 01: 16mhz 10: 12mhz 11: 8mhz bit 3~2 unimplemented, read as "0" bit 1~0 d1, d0 : these bits must be set to the binary value "00" external 32.768khz crystal oscillator C lxt (bs85c20-5 only) for the bs85c20-5, there is an additional external 32.768khz crystal oscillator that is used as a clock source for t ime base. this clock source has a fixed frequency of 32.768khz and requires a 32.768khz crystal to be connected between pins osc1 and osc2. the external resistor and capacitor components connected to the 32.768khz crystal are necessary to provide oscillation. for applications where precise frequencies are essential, these components may be required to provide frequency compen sation due to dif ferent crystal manufacturing toleranc es. during power -up there is a time delay associated with the lxt oscillator waiting for it to start-up and stabilise. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specifcation. the external parallel feedback resistor, rp, is normally required.
? ??? ?? -? -? external lxt oscillator lxt oscillator c1 and c2 values crystal frequency c1 c2 32.768khz 10pf 10pf note:1. c1 and c2 val ? es are for ?? idance only. 2. r p = 5m~10m is recommended. 32.768khz crystal recommended capacitor values
rev. 1.20 44 ???? st 10 ? 2012 rev. 1.20 45 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver lxt oscillator low power function (bs85c20-5 only) the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the tbc register. lxtlp bit lxt mode 0 q ? ick start 1 low-power after po wer on t he l xtlp bi t, i t wi ll be a utomatically c leared t o z ero e nsuring t hat t he l xt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up a nd st abilise q uickly. ho wever, a fter t he l xt osc illator h as fu lly po wered u p i t c an be placed into the low-power mode by setting the lxtlp bit high. the oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it should be noted that, no matter what condition the lxtlp bit is set to, the lxt oscillator will be always function normally , the only dif ference is that it will take more time to start up if it is in the low-power mode. internal low speed rc oscillator C lirc the internal 32khz system oscillator is the low frequency oscillator . it is a fully integrated rc osc illator wi th a t ypical fre quency of 32khz a t 5v , re quiring no e xternal c omponents for i ts implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. after power on this lirc oscillator will be permanently enabled; there is no provision to disable the oscillator using register bits. operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red port able a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided thes e devices with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the main system clock, can come from either a high frequency , f h , or low frequency , f l , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register . both the high and low speed system cloc ks are sourced from internal rc oscillators. for bs85c20-5, the t ime base 0/1 is sourced from lxt or f sys /4.
rev. 1.20 44 ????st 10? 2012 rev. 1.20 45 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver
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rev. 1.20 46 ???? st 10 ? 2012 rev. 1.20 47 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver control register a single register, smod, is used for overall control of the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 name cks2 cks1 cks0 d4 lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7~5 cks2~cks0 : the system clock selection when hlclk is "0" 000: f (f lirc ) 001: f (f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which is lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 undefned bit these bits can be read or written by user software program. bit 3 lto : low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscilla tor ready fag which indicates when the low speed system oscillator is stable after power on reset. bit 2 hto : high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this fag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as "1" by the application program after device power -on. the fag will be low when in the sleep or idle0 mode but after a wake-up has occurred, the fag will change to a high level after 15~16 clock cycles. bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the hal t instruction is executed. if this bit is high, when a hal t instruction is executed the device wi ll e nter t he i dle mo de. i n t he i dle1 mo de t he c pu wi ll st op r unning but t he syst em c lock wi ll c ontinue t o ke ep t he pe ripheral fun ctions ope rational, i f fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a hal t instruction is executed. bit 0 hlclk : system clock selection 0: f h /2 ~ f h /64 or f 1: f h this bit is used to select if the f h clock or the f h /2 ~ f h /64 or fl clock is used as the system clock. when the bit is high the fh clock will be selected and if low the f h /2 ~ h /64 or f clock will be selected. when system clock switches from the f h clock to the clock and the f h clock will be automatically switched off to conserve power .
rev. 1.20 46 ????st 10? 2012 rev. 1.20 47 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver system operation modes there a re f ive d ifferent m odes o f o peration f or t he m icrocontroller, e ach o ne wi th i ts o wn special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, the normal mode and slow mode. the remaining three modes, the sleep , idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operation mode description cpu f sys f lirc f tbc norm ? l mode on f h~ fh/64 on on slow mode on f l on on idle0 mode off off on on idle1 mode off on on on sleep mode off off on off normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator . the high speed oscilla tor will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register . although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the micr ocontroller operates normally altho ugh now with the slow speed clock source. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the high speed clock is off. sleep mode the sleep mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is low . in the sleep mode the cpu will be stopped however as the f lirc oscillator continues to run the w atchdog t imer will continue to operate. idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the wdtc register is low . in the idle0 mode the system oscillator the system oscillator will be stopped and will therefo re be inhibited from driving the cpu. idle1 mode the idle1 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the wdtc register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be the high speed or low speed system oscillator.
rev. 1.20 48 ???? st 10 ? 2012 rev. 1.20 49 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver

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operating mode switching the devi ce c an swi tch bet ween opera ting m odes dynam ically al lowing t he use r t o se lect t he best performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the hal t instruction. when a hal t instructio n is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the wdtc register. when t he hl clk b it swi tches t o a l ow l evel, whi ch i mplies t hat c lock so urce i s swi tched fr om the high speed clock source, f hirc , to the clock source, f hirc /2~f hirc /64 or f lirc . if the clock is from f hirc , the high speed clock source will stop running to conserve power . when this happens it must be noted that the f hirc /16 and f hirc /64 internal clock sources will also stop running. the accompanying fowchart shows what happens when the device moves between the various operating modes.
rev. 1.20 48 ????st 10? 2012 rev. 1.20 49 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver
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? - ? ?? ? ?? ? ? ? ?? ? ?? ? ? ? ?? ? ?? normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to "0" and set the cks2~cks0 bits to "000" or "001" in the smod register . this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode clock is sourced from the lirc oscillator. slow mode to normal mode switching in slow mode the system uses the lirc low speed system oscillator . t o switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to "1" or hlclk bit is " 0", but cks2~cks0 is set to " 010", " 011", " 100", " 101", " 110" or " 111". as a cert ain amount of time will be required for the high frequency clock to stabilise, the status of the ht o bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. entering the sleep mode there is only one way for the device to enter the sleep mode and that is to execute the "hal t" instruction in the application program with the idlen bit in smod register equal to "0". when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the "halt" instruction, but the f lirc clock will be on ? the data memory contents and registers will maintain their present condition ? the wdt will be cleared and resume counting ? the i/o ports will maintain their present conditions ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared
rev. 1.20 50 ???? st 10 ? 2012 rev. 1.20 51 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the " halt" instruction in the application program with the idlen bit in smod register equal to "1" and the fsyson bi t in wdtc register equal to "0". when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the "halt" i nstruction, but the t ime base clock and flirc c lock w ill b e o n ? the data memory contents and registers will maintain their present condition ? the wdt will be cleared and resume counting ? the i/o ports will maintain their present conditions ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the " halt" instruction in the application program with the idlen bit in smod register equal to "1" and the fsyson bit in wdtc register equal to "1". when this instruction is executed under the with conditions described above, the following will occur: ? the system clock and f lirc clock will be on and the application program will stop at the "halt" instruction ? the data memory contents and registers will maintain their present condition ? the wdt will be cleared and resume counting ? the i/o ports will maintain their present conditions ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode , t here a re ot her c onsiderations whi ch m ust a lso be t aken i nto a ccount by t he c ircuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have dif ferent package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro- amps.
rev. 1.20 50 ????st 10? 2012 rev. 1.20 51 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external reset ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the t o and pdf flags. the pdf flag is cleared by a system po wer-up or e xecuting t he c lear w atchdog t imer i nstructions a nd i s se t wh en e xecuting the "hal t" instruction. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wil l resume exec ution at the i nstruction f ollowing t he "hal t" instruction. if the system is woken up by an interrupt, then two p ossible si tuations m ay o ccur. t he fr st i s wh ere t he r elated i nterrupt i s d isabled o r t he i nterrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "hal t" instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request fag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled. system oscillator wake-up time (sleep mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hirc 15~16 hirc cycles 1~2 hirc cycles lirc 1~2 lirc cycles 1~2 lirc cycles wake-up times programming considerations the high speed and low speed oscillators both use the same sst counter . for example, if the system is woken up from the sleep mode the hirc oscillator needs to start-up from an off state. ? if the device is woken up from the sleep mode to the normal mode, the high speed system oscillator needs an sst period. the device will execute the frst instruction after hto is high.
rev. 1.20 52 ???? st 10 ? 2012 rev. 1.20 53 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer c lock source i s provi ded by t he i nternal l ow spe ed osc illator, f lirc . t he watchdog t imer source clock is then subdivided by a ratio of 2 8 to 2 15 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register . the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v. however, it should be noted that this specifed internal clock period can vary with vdd, temperature and process variations. watchdog timer control register a single register, wdtc, controls the required timeout period. wdtc register bit 7 6 5 4 3 2 1 0 name fsyson ws2 ws1 ws0 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 1 1 1 0 1 0 bit 7 fsyson : f control in idle mode 0: disable 1: enable bit 6~4 ws2, ws1, ws0 : wdt time-out period selection 000: 256/f lirc 001: 512/f lirc 010: 1024/f lirc 011: 2048/f lirc 100: 4096/f lirc 101: 8192/f lirc 110: 16384/f lirc 111: 32768/f lirc these three bits determine the divis ion ratio of the w atchdog t imer s ource clock, which in turn determines the timeout period. bit 3~0 undefned bit these bits can be read or written by user software program.
rev. 1.20 52 ????st 10? 2012 rev. 1.20 53 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver watchdog timer operation in these devices the w atchdog t imer supplied by the f lirc oscillator and is therefore always on. the watchdog t imer operates by providing a device reset when its timer overfows. this means that in the application program and during normal operation the user has to strategically clear the w atchdog timer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the c lear wa tchdog i nstructions. if t he progra m m alfunctions for wha tever re ason, j umps t o an unkown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the w atchdog t imer will overfow and reset the device. under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the w atchdog t imer. the first is an external hardware reset, the second is using the w atchdog t imer software clear instructions and the third is via a hal t instruction. the w atchdog t imer is cleared using a single clr wdt instruction. the m aximum t ime out pe riod i s wh en t he 2 15 di vision ra tio i s se lected. as a n e xample, wi th t he lirc oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 2 15 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration.

? ? ?? ? ? ? ? ? - ? ?? watchdog timer
rev. 1.20 54 ???? st 10 ? 2012 rev. 1.20 55 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short del ay, will be in a well defined state and ready to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is w hen the w atchdog t imer overflow s and resets the microcontroller . a ll types of reset operations result in different register conditions being setup. another reset exists in the form of a low v oltage reset, l vr, where a full reset, is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are several w ays in w hich a microcontroller res et can occur , through events occurring both internally and externally: power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset als o ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. note: t rstd is power-on delay, typical time=100ms power-on reset timing chart low voltage reset C lvr if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery , the l vr will automatically reset the device internally . the l vr includes the following spe cifications: for a val id l vr si gnal, a l ow volt age, i .e., a volt age i n t he range bet ween 0.9v~v lvr must exist for greater than the value t lvr specifed in the a.c. characteristics. if the low voltage state does not exceed t lvr , the l vr will ignore it and will not perform a reset function. o ne o f a r ange of specifed voltage values for v lvr can be selected using confguration options. the l vr function is permanently on in these devices. note: t rstd is power-on delay, typical time=100ms low voltage reset timing chart
rev. 1.20 54 ????st 10? 2012 rev. 1.20 55 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver watchdog time-out reset during normal operation the w atchdog t ime-out r eset d uring n ormal o peration i s t he sa me a s a h ardware p ower-on r eset except that the w atchdog time-out fag t o will be set to "1". note: t rstd is power-on delay, typical time=100ms wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cleared to "0" and the t o fag will be set to "1". refer to the a.c. characteristics for t sst details. note: the t sst is 15~16 clock cycles if the system clock source is provided by hirc. the t sst is 1~2 clock for lirc. wdt time-out reset during sleep or idle timing chart reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus regis ter and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: to pdf reset conditions 0 0 power-on reset ? ? lvr reset d ? rin ? norm ? l or slow mode operation 1 ? wdt time-o ? t reset d ? rin ? norm ? l or slow mode operation 1 1 wdt time-o ? t reset d ? rin ? idle or sleep mode operation note: "u" stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset pro ? ram co ? nter reset to zero interr ? pts ? ll interr ? pts will be disabled wdt clear after reset ? wdt be ? ins co ? ntin ? timer mod ? les timer co ? nter will be t ? rned off inp ? t/o ? tp ? t ports i/o ports will be set ? p as inp ? ts stack pointer stack pointer will point to the top of the stack
rev. 1.20 56 ???? st 10 ? 2012 rev. 1.20 57 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver the dif ferent kinds of resets all af fect the internal registers of the microcontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will refect the situation for the larger package type. register bs85b12-3 /bs85b20-5 bs85b20-3 power-on reset lvr reset time-out (normal operation) time-out (idle or sleep) mp0 ? ? x x x x x x x x ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mp1 ? ? x x x x x x x x ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bp ? - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - ? bp ? - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - ? ? ? cc ? ? x x x x x x x x ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pcl ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tblp ? ? x x x x x x x x ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tblh ? ? - x x x x x x x - ? ? ? ? ? ? ? - ? ? ? ? ? ? ? - ? ? ? ? ? ? ? tbhp ? - - - - - x x x - - - - - ? ? ? - - - - - ? ? ? - - - - - ? ? ? tbhp ? - - - - x x x x - - - - ? ? ? ? - - - - ? ? ? ? - - - - ? ? ? ? ? ? - - 0 0 x x x x - - ? ? ? ? ? ? - - 1 ? ? ? ? ? - - 1 1 ? ? ? ? smod ? ? 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 ? ? ? ? ? ? ? ? lvdc ? ? - -0 0 - 0 0 0 - -0 0 - 0 0 0 - -0 0 - 0 0 0 - - ? ? - ? ? ? integ ? ? - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - ? ? ? ? wdtc ? ? 0 1 1 1 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 1 0 1 0 ? ? ? ? ? ? ? ? tbc ? ? 0 0 1 1 0 1 1 1 0 0 1 1 0 1 1 1 0 0 1 1 0 1 1 1 ? ? ? ? ? ? ? ? ? ? - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - ? ? ? ? ? ? ? intc1 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? intc2 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? intc3 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? mfi0 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? mfi1 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? mfi2 ? ? - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - ? ? ? - ? ? ? mfi3 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? p ? w u ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? p ? pu ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? p ? ? ? 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ? ? ? ? ? ? ? ? p ? c ? ? 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ? ? ? ? ? ? ? ? pbpu ? - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - ? ? ? ? ? ? pbpu ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? pb ? - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - ? ? ? ? ? ? pb ? 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ? ? ? ? ? ? ? ? pbc ? - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - ? ? ? ? ? ? pbc ? 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ? ? ? ? ? ? ? ? pcpu ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? pc ? ? 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ? ? ? ? ? ? ? ? pcc ? ? 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ? ? ? ? ? ? ? ? pdpu ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? pd ? 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ? ? ? ? ? ? ? ? pdc ? 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ? ? ? ? ? ? ? ?
rev. 1.20 56 ????st 10? 2012 rev. 1.20 57 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver register bs85b12-3 /bs85b20-5 bs85b20-3 power-on reset lvr reset time-out (normal operation) time-out (idle or sleep) pepu ? - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - ? ? ? ? ? ? pe ? - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - ? ? ? ? ? ? pec ? - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - ? ? ? ? ? ? slcdc0 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? slcdc1 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? slcdc2 ? - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - ? ? ? ? ? ? slcdc2 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? slcdc3 ? 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 ? - ? ? ? ? ? ? sledc0 ? - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - ? ? ? ? ? ? sledc0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? sledc1 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? sledc2 ? - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - ? ? ? ? ? ? mfi4 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? mfi5 ? - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - ? ? - - ? ? i2ctoc ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? simc0 ? ? 1 1 1 0 0 0 0 - 1 1 1 0 0 0 0 - 1 1 1 0 0 0 0 - ? ? ? ? ? ? ? - simc1 ? ? 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ? ? ? ? ? ? ? ? simd ? ? x x x x x x x x x x x x x x x x x x x x x x x x ? ? ? ? ? ? ? ? sim ? / simc2 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tm0c0 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tm0c1 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tm0dl ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tm0dh ? ? - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - ? ? tm0 ? l ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tm0 ? h ? ? - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - ? ? ee ? ? ? ? 0 0 0 0 0 0 ? ? 0 0 0 0 0 0 ? ? 0 0 0 0 0 0 ? ? u u u u u u ee ? ? ? 0 0 0 0 0 0 0 ? 0 0 0 0 0 0 0 ? 0 0 0 0 0 0 0 ? u u u u u u u eed ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tmpc0 ? ? 1 0 0 1 ? ? 0 1 1 0 0 1 ? ? 0 1 1 0 0 1 ? ? 0 1 u u u u ? ? u u tmpc1 ? - - - - - - 0 1 - - - - - - 0 1 - - - - - - 0 1 - - - - - - ? ? prm0 ? - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ? - ? - ? - ? prm0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? prm1 ? 0 0 0 0 - 0 - 0 0 0 0 0 - 0 - 0 0 0 0 0 - 0 - 0 ? ? ? ? - ? - ? prm1 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? prm2 ? 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 ? ? ? ? - - ? ? prm2 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tm1c0 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tm1c1 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tm1c2 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tm1dl ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tm1dh ? ? - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - ? ? tm1 ? l ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tm1 ? h ? ? - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - ? ? tm1bl ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ?
rev. 1.20 58 ???? st 10 ? 2012 rev. 1.20 59 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver register bs85b12-3 /bs85b20-5 bs85b20-3 power-on reset lvr reset time-out (normal operation) time-out (idle or sleep) tm1bh ? ? - - - - - -0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - ? ? tm2c0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tm2c1 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tm2dl ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tm2dh ? - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - ? ? tm2 ? l ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tm2 ? h ? - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - ? ? ctrl ? ? - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - ? ? - - ? ? tkm016dh ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm016dl ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm0c0 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm0c1 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm0c2 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm0c3 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm116dh ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm116dl ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm1c0 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm1c1 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm1c2 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm1c3 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm216dh ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm216dl ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm2c0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm2c1 ? ? 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - ? ? ? ? - - - - tkm2c2 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm2c3 ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm316dh ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm316dl ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm3c0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm3c1 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm3c2 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm3c3 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm416dh ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm416dl ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm4c0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm4c1 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm4c2 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? tkm4c3 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? eec ? ? - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - ? ? ? ? note: "u" stands for unchanged "x" stands for unknown "-" stands for unimplemented
rev. 1.20 58 ????st 10? 2012 rev. 1.20 59 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names p a~pe. these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction "mov a,[m]", where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o register list bs85b12-3 register name bit 7 6 5 4 3 2 1 0 p ? w u d7 d6 d5 d4 d3 d2 d1 d0 p ? pu d7 d6 d5 d4 d3 d2 d1 d0 p ? d7 d6 d5 d4 d3 d2 d1 d0 p ? c d7 d6 d5 d4 d3 d2 d1 d0 pbpu d5 d4 d3 d2 d1 d0 pb d5 d4 d3 d2 d1 d0 pbc d5 d4 d3 d2 d1 d0 pcpu d7 d6 d5 d4 d3 d2 d1 d0 pc d7 d6 d5 d4 d3 d2 d1 d0 pcc d7 d6 d5 d4 d3 d2 d1 d0 bs85c20-3/bs85c20-5 register name bit 7 6 5 4 3 2 1 0 p ? w u d7 d6 d5 d4 d3 d2 d1 d0 p ? pu d7 d6 d5 d4 d3 d2 d1 d0 p ? d7 d6 d5 d4 d3 d2 d1 d0 p ? c d7 d6 d5 d4 d3 d2 d1 d0 pbpu d7 d6 d5 d4 d3 d2 d1 d0 pb d7 d6 d5 d4 d3 d2 d1 d0 pbc d7 d6 d5 d4 d3 d2 d1 d0 pcpu d7 d6 d5 d4 d3 d2 d1 d0 pc d7 d6 d5 d4 d3 d2 d1 d0 pcc d7 d6 d5 d4 d3 d2 d1 d0 pdpu d7 d6 d5 d4 d3 d2 d1 d0 pd d7 d6 d5 d4 d3 d2 d1 d0 pdc d7 d6 d5 d4 d3 d2 d1 d0 pepu d5 d4 d3 d2 d1 d0 pe d5 d4 d3 d2 d1 d0 pec d5 d4 d3 d2 d1 d0
rev. 1.20 60 ???? st 10 ? 2012 rev. 1.20 61 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high re sistors a re se lected u sing t he re gister p apu~pepu, a nd a re i mplemented u sing we ak pmos transistors. bs85b12-3: papu, pcpu registers bs85c20-3/bs85c20-5: papu, pbpu, pcpu, pdpu registers bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 pxpu : port bit 7~bit 0 pull-high control 0: disable 1: enable bs85b12-3: pbpu registers bs85c20-3/bs85c20-5: pepu registers bit 7 6 5 4 3 2 1 0 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~4 unimplemented, read as "0" bit 3~0 pxpu : port bit 5~bit 0 pull-high control 0: disable 1: enable port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~5 unimplemented, read as "0" bit 4~0 paw u : port a bit 7~bit 0 wake-up control 0: disable 1: enable
rev. 1.20 60 ????st 10? 2012 rev. 1.20 61 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver i/o port control register the i/o port has its own control register known as p ac~pec, to control the input/output configuration. w ith this control register , each cmos output or input can be reconfigured dynamically under softw are control. each pin of the i/o port is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a "1". this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a "0", the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however , it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. bs85b12-3: pac, pcc registers bs85c20-3/bs85c20-5: pac, pbc, pcc, pdc registers bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 pxc : i/o port bit 7 ~ bit 0 input/output control 0: output 1: input bs85b12-3: pbc registers bs85c20-3/bs85c20-5: pec registers bit 7 6 5 4 3 2 1 0 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 1 1 bit 7~4 unimplemented, read as "0" bit 3~0 pxc : port bit 5~bit 0 input/output control 0: output 1: input pin re-mapping functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by suppl ying pi ns wi th m ulti-functions, m any of t hese di fficulties c an be ove rcome. t he wa y i n which the pin function of each pin is selected is dif ferent for each function and a priority order is established where more tha n one pin func tion is se lected si multaneously. addit ionally the re are a series of prm0, prm1 and prm2 registers to establish certain pin functions. pin-remapping registers the limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several dif ferent functions and providing a means of function selection, a wide range of dif ferent functions can be incorporated into even relatively small package sizes. the device includes prm0, prm1, prm2 registers which can select the functions of certain pins.
rev. 1.20 62 ???? st 10 ? 2012 rev. 1.20 63 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver pin-remapping register list ? bs85b12-3 register name bit 7 6 5 4 3 2 1 0 prm0 scsps0 sdips0 sckps0 sdops0 prm1 int1ps int0ps tck1ps tck0ps pints0 pckps0 prm2 tp1b2ps tp1b1ps tp1b0ps tp1 ? ps tp01ps tp00ps ? bs85c20-3/bs85c20-5 register name bit 7 6 5 4 3 2 1 0 prm0 scsps1 scsps0 sdips1 sdips0 sckps1 sckps0 sdops1 sdops0 prm1 int1ps int0ps tck1ps tck0ps pints1 pints0 pckps1 pckps0 prm2 tp1b2ps tp1b1ps tp1b0ps tp1 ? ps tp21ps tp20ps tp01ps tp00ps slcdc3 tck2ps seg21en seg20en seg19en seg18en seg17en seg16en prm0 register C bs85b12-3 bit 7 6 5 4 3 2 1 0 name scsps0 sdips0 sckps0 sdops0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 scsps0 : scs pin remapping control 0: scs on pa3 1: scs on pc3 bit 5 unimplemented, read as "0" bit 4 sdips0 : sdi/sda pin remapping control 0: sdi/sda on pa0 1: sdi/sda on pc2 bit 3 unimplemented, read as "0" bit 2 sckps0 : sck/scl pin remapping control 0: sck/scl on pa2 1: sck/scl on pc1 bit 1 unimplemented, read as "0" bit 0 sdops0 : sdo pin remapping control 0: sdo on pa7 1: sdo on pc0
rev. 1.20 62 ????st 10? 2012 rev. 1.20 63 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver prm0 register C bs85c20-3/bs85c20-5 bit 7 6 5 4 3 2 1 0 name scsps1 scsps0 sdips1 sdips0 sckps1 sckps0 sdops1 sdops0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 scsps1~scsps0 : scs pin remapping control 00: scs on pa3 01: scs on pc3 10: scs on pe2 11: undefned bit 5~4 sdips1~sdips0 : sdi/sda pin remapping control 00: sdi/sda on pa0 01: sdi/sda on pc2 10: sdi/sda on pe4 11: undefned bit 3~2 sckps1~sckps0 : sck/scl pin remapping control 00: sck/scl on pa2 01: sck/scl on pc1 10: sck/scl on pe3 11: undefned bit 1~0 sdops1~sdops0 : sdo pin remapping control 00: sdo on pa7 01: sdo on pc0 10: sdo on pe5 11: undefned prm1 register C bs85b12-3 bit 7 6 5 4 3 2 1 0 name int1ps int0ps tck1ps tck0ps pints0 pckps0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 int1ps : int1 pin remapping control 0: int1 on pa1 1: int1 on pc5 bit 6 int0ps : int0 pin remapping control 0: int0 on pa4 1: int0 on pc4 bit 5 tck1ps : tck1 pin remapping control 0: tck1 on pa1 1: tck1 on pc5 bit 4 tck0ps : tck0 pin remapping control 0: tck0 on pa4 1: tck0 on pc4 bit 3 unimplemented, read as "0" bit 2 pints0 : pint pin remapping control 0: pint on pb5 1: pint on pc7 bit 1 unimplemented, read as "0" bit 0 pckps0 : pck pin remapping control 0: pck on pb4 1: pck on pc6
rev. 1.20 64 ???? st 10 ? 2012 rev. 1.20 65 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver prm1 register C bs85c20-3/bs85c20-5 bit 7 6 5 4 3 2 1 0 name int1ps int0ps tck1ps tck0ps pints1 pints0 pckps1 pckps0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 int1ps : int1 pin remapping control 0: int1 on pa1 1: int1 on pc5 bit 6 int0ps : int0 pin remapping control 0: int0 on pa4 1: int0 on pc4 bit 5 tck1ps : tck1 pin remapping control 0: tck1 on pa1 1: tck1 on pc5 bit 4 tck0ps : tck0 pin remapping control 0: tck0 on pa4 1: tck0 on pc4 bit 3~2 pints1~pints0 : pint pin remapping control 00: pint on pb5 01: pint on pc7 10: pint on pe0 11: undefned bit 1~0 pckps1~pckps0 : pck pin remapping control 00: pck on pb4 01: pck on pc6 10: pck on pe1 11: undefned prm2 register C bs85b12-3 bit 7 6 5 4 3 2 1 0 name tp1b2ps tp1b1ps tp1b0ps tp1 ? ps tp01ps tp00ps r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 tp1b2ps : tp1b_2 pin remapping ccontrol 0: tp1b_2 on pb4 1: tp1b_2 on pc4 bit 6 tp1b1ps : tp1b_1 pin remapping control 0: tp1b_1 on pb3 1: tp1b_1 on pc3 bit 5 tp1b0ps : tp1b_0 pin remapping control 0: tp1b_0 on pb2 1: tp1b_0 on pc2 bit 4 tp1aps : tp1a pin remapping control 0: tp1a on pb5 1: tp1a on pc5 bit 3~2 unimplemented, read as "0" bit 1 tp01ps : tp0_1 pin remapping control 0: tp0_1 on pb1 1: tp0_1 on pc1 bit 0 tp00ps : tp0_0 pin remapping control 0: tp0_0 on pb0 1: tp0_0 on pc0
rev. 1.20 64 ????st 10? 2012 rev. 1.20 65 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver prm2 register C bs85c20-3/bs85c20-5 bit 7 6 5 4 3 2 1 0 name tp1b2ps tp1b1ps tp1b0ps tp1 ? ps tp21ps tp20ps tp01ps tp00ps r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tp1b2ps : tp1b_2 pin remapping control 0: tp1b_2 on pb4 1: tp1b_2 on pc4 bit 6 tp1b1ps : tp1b_1 pin remapping control 0: tp1b_1 on pb3 1: tp1b_1 on pc3 bit 5 tp1b0ps : tp1b_0 pin remapping control 0: tp1b_0 on pb2 1: tp1b_0 on pc2 bit 4 tp1aps : tp1a pin remapping coontrol 0: tp1a on pb5 1: tp1a on pc5 bit 3 tp21ps : tp2_1 pin remapping coontrol 0: tp2_1 on pb2 1: tp2_1 on pe2 bit 2 tp20ps : tp2_0 pin remapping coontrol 0: tp2_0 on pb1 1: tp2_0 on pe1 bit 1 tp01ps : tp0_1 pin remapping coontrol 0: tp0_1 on pb1 1: tp0_1 on pc1 bit 0 tp00ps : tp0_0 pin remapping coontrol 0: tp0_0 on pb0 1: tp0_0 on pc0 slcdc3 register C bs85c20-3/bs85c20-5 bit 7 6 5 4 3 2 1 0 name tck2ps seg21en seg20en seg19en seg18en seg17en seg16en r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 tck2ps : tck2 pin remapping control 0: tck2 on pc6 1: tck2 on pd0 bit 6 unimplemented, read as "0" bit 5~0 described elsewhere
rev. 1.20 66 ???? st 10 ? 2012 rev. 1.20 67 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.

??? ? ? ? ?? generic input/output structure programming considerations within the user program, one of the frst things to consider is port initi alisation. after a reset, all of the i/o data and port control register will be set high. this means that all i/o pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. if the port control register , p ac~pec, is then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data register , p a~pe, is first programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "set [m].i" and "clr [m].i" instructions . n ote that w hen us ing thes e bit control instructions , a read-modify-w rite operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.
rev. 1.20 66 ????st 10? 2012 rev. 1.20 67 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. t o implement time related functions each device includes several t imer modules, abbreviated t o t he na me t m. t he t ms a re m ulti-purpose t iming un its a nd se rve t o pr ovide operations such as t imer/counter, input capture, compare match output and single pulse output as well as being the functional unit for the generation of pwm signals. each of the tms has either two o r t hree i ndividual i nterrupts. t he a ddition o f i nput a nd o utput p ins f or e ach t m e nsures t hat users are provided with timing units with a wide and fexible range of features. the common features of the dif ferent tm types are described here with more detailed information provided in the individual compact, standard and enhanced tm sections. introduction the devices contain from two to three tms depending upon which device is selected with each tm having a reference name of tm0, tm1 and tm2. each individual tm can be categorised as a certain type, namely compact t ype tm, standard t ype tm or enhanced t ype tm. although similar in nature, the dif ferent tm types vary in their feature complexity . the common features to a ll of t he com pact, st andard a nd e nhanced t ms wi ll be de scribed i n t his se ction, t he de tailed operation regardin g each of the tm types will be described in separate sections. the main features and differences between the three types of tms are summarised in the accompanying table. function ctm stm etm timer/co ? nter i/p capt ? re compare match o ? tp ? t pwm channels 1 1 2 sin ? le p ? lse o ? tp ? t 1 2 pwm ? li ? nment ed ? e ed ? e ed ? e & centre pwm ? dj ? stment period & d ? ty d ? ty or period d ? ty or period d ? ty or period tm function summary each device in the series contains a specifc number of either compact t ype, standard t ype and enhanced t ype tm units which are shown in the table together with their individual reference name, tm0~tm2. device tm0 tm1 tm2 bs85b12-3 10-bit ctm 10-bit etm bs85c20-3 /bs85c20-5 10-bit ctm 10-bit etm 10-bit stm tm name/type reference tm operation the three dif ferent types of tm of fer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a fre e runni ng c ounter who se va lue i s t hen c ompared wi th t he va lue of pre -programmed i nternal comparators. when the free running counter has the same value as the pre-programmed comparator , known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch c an c lear t he counter a nd pe rhaps a lso c hange t he c ondition of t he t m ou tput pi n. t he i nternal t m c ounter i s driven by a user selectable clock source, which can be an internal clock or an external pin.
rev. 1.20 68 ???? st 10 ? 2012 rev. 1.20 69 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver tm clock source the c lock so urce wh ich d rives t he m ain c ounter i n e ach t m c an o riginate f rom v arious so urces. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f tbc clock source or the external tckn pin. note that setti ng these bits to the value 101 will selec t a reserved clock input, in ef fect disconnecting the tm clock source. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the compact and standard type tms each have two internal interrupts, one for each of the internal comparator a or comparator p , which generate a tm interrupt when a compare match condition occurs. as the enhanced type tm has three internal comparators and comparator a or comparator b or comparator p compare match functions, it consequently has three internal interrupts. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register . this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm i f se lected u sing t he t nck2~tnck0 b its. t he t m i nput p in c an b e c hosen t o h ave e ither a rising or falling active edge. the tms each have one or more output pins with the label tpn. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the p wm output w aveform. a s the tm output pins are pin-s hared w ith other function, the tm output function must first be setup using registers. a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. the number of output pins for each tm type and device is dif ferent, the details are provided in the accompanying table. all tm output pin names have an "_n" suffx. pin names that include a "_1" or "_2" suffx indicate that they are from a tm with multiple output pins. this allows the tm to generate a complimentary output pair, selected using the i/o register data bits. device ctm stm etm registers bs85b12-3 tp0_0 ? tp0_1 tp1 ?? tp1b_0 ? tp1b_1 ? tp1b_2 tmpc0 bs85c20-3 /bs85c20-5 tp0_0 ? tp0_1 tp2_0 ? tp2_1 tp1 ?? tp1b_0 ? tp1b_1 ? tp1b_2 tmpc0 ? tmpc1 tm output pins
rev. 1.20 68 ????st 10? 2012 rev. 1.20 69 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver tm input/output pin control registers selecting to have a tm input/outpu t or whether to retain its other shared function, is implemented using one or two registers, with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output, if reset to zero the pin will retain its original other function. registers device bit 7 6 5 4 3 2 1 0 tmpc0 ? ll t1 ? cp0 t1bcp2 t1bcp1 t1bcp0 t0cp1 t0cp0 tmpc0 bs85c20-3 /bs85c20-5 t2cp1 t2cp0 tm input/output pin control registers list tmpc0 register C all devices bit 7 6 5 4 3 2 1 0 name t1 ? cp0 t1bcp2 t1bcp1 t1bcp0 t0cp1 t0cp0 r/w r/w r/w r/w r/w r/w r/w por 1 0 0 1 0 1 bit 7 t1acp0 : tp1a pin control 0: disable 1: enable bit 6 t1bcp2 : tp1b_2 pin control 0: disable 1: enable bit 5 t1bcp1 : tp1b_1 pin control 0: disable 1: enable bit 4 t1bcp0 : tp1b_0 pin control 0: disable 1: enable bit 3~2 unimplemented, read as "0" bit 1 t0cp1 : tp0_1 pin control 0: disable 1: enable bit 0 t0cp0 : tp0_0 pin control 0: disable 1: enable tmpc1 register C bs85c20-3/bs85c20-5 bit 7 6 5 4 3 2 1 0 name t2cp1 t2cp0 r/w r/w r/w por 0 1 bit 7~2 unimplemented, read as "0" bit 1 t2cp1 : tp2_1 pin control 0: disable 1: enable bit 0 t2cp0 : tp2_0 pin control 0: disable 1: enable
rev. 1.20 70 ???? st 10 ? 2012 rev. 1.20 71 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver

tm0 function pin control block diagram note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input.
tm2 function pin control block diagram C bs85c20-3/bs85c20-5 only note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input.
rev. 1.20 70 ????st 10? 2012 rev. 1.20 71 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver

tm1 function pin control block diagram note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input.
rev. 1.20 72 ???? st 10 ? 2012 rev. 1.20 73 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver programming considerations the tm counter registers and the capture/compare ccra and ccrb registers, being either 10- bit or 16-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specifc way . the important point to note is that data transfer to and from the 8-bit buf fer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed.

as the ccra and ccrb registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specifc way as described above, it is recommended to use the "mov" instruction to access the ccra and ccrb low byte registers, named tm xal and tmxbl, using the following access procedures. accessing the ccra or ccrb low byte registers without following these access procedures will result in unpredictable values. the following steps show the read and write procedures: ? writing data to ccrb or ccra ? step 1. w rite data to low byte tmxal or tmxbl C note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte tmxah or tmxbh C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccrb or ccra ? step 1. read data from the high byte tmxdh, tmxah or tmxbh C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl, tmxal or tmxbl C this step reads data from the 8-bit buffer.
rev. 1.20 72 ????st 10? 2012 rev. 1.20 73 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver compact type tm C ctm although the simplest form of the three tm types, the compact tm type still contains three operating modes, which are compare match output, t imer/event counter and pwm output modes. the compact tm can also be controlled with an external input pin and can drive one or two external output pins. these two external output pins can be the same signal or the inverse signal. ctm name tm no. tm input pin tm output pin bs85b12-3 10-bit ctm 0 tck0 tp0_0 ? tp0_1 bs85c20-3 /bs85c20-5 10-bit ctm 0 tck0 tp0_0 ? tp0_1 compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a a nd com parator p. t hese c omparators wi ll c ompare t he v alue i n t he c ounter wi th c crp a nd c cra r egisters. t he ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
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rev. 1.20 74 ???? st 10 ? 2012 rev. 1.20 75 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver compact type tm register description overall operat ion of t he compa ct tm i s cont rolled usi ng si x regi sters. a rea d only regi ster pai r exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmnc0 tnp ? u tnck2 tnck1 tnck0 tnon tnrp2 tnrp1 tnrp0 tmnc1 tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr tmndl d7 d6 d5 d4 d3 d2 d1 d0 tmndh d9 d8 tmn ? l d7 d6 d5 d4 d3 d2 d1 d0 tmn ? h d9 d8 compact tm register list (n=0) tmndl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tmndl : tmn counter low byte register bit 7 ~ bit 0 tmn 10-bit counter bit 7 ~ bit 0 tmndh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tmndh : tmn counter high byte register bit 1 ~ bit 0 tmn 10-bit counter bit 9 ~ bit 8 tmnal register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tmnal : tmn ccra low byte register bit 7 ~ bit 0 tmn 10-bit ccra bit 7 ~ bit 0 tmnah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tmn 10-bit ccra bit 9 ~ bit 8
rev. 1.20 74 ????st 10? 2012 rev. 1.20 75 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver tmnc0 register bit 7 6 5 4 3 2 1 0 name tnp ? u tnck2 tnck1 tnck0 tnon tnrp2 tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tnpau : tmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0 : select tmn counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f tbc 101: undefned 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tm. selectin g the reserved clock input will ef fectively disable the internal counter . the external pin clock source can be chosen to be act ive on the rising or falling edge . the cl ock source f is the system c lock, wh ile f h a nd f tbc a re o ther i nternal c locks, t he d etails o f wh ich c an b e found in the oscillator section. bit 3 tnon : tmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, cle aring the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value w ill be res et to zero, however when the bit changes from high to low , the internal counter will retain its residual value. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high. bit 2~0 tnrp2~tnrp0 : tmn ccrp 3-bit register, compared with the tmn counter bit 9~bit 7 comparator p match period 000: 1024 tmn clocks 001: 128 tmn clocks 010: 256 tmn clocks 011: 384 tmn clocks 100: 512 tmn clocks 101: 640 tmn clocks 110: 768 tmn clocks 111: 896 tmn clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are t hen c ompared wi th t he i nternal c ounter's h ighest t hree b its. t he r esult o f t his comparison can be selected to clear the internal counter if the tncclr bit is set to zero. setting the tncclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overfow at its maximum value.
rev. 1.20 76 ???? st 10 ? 2012 rev. 1.20 77 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver tmnc1 register bit 7 6 5 4 3 2 1 0 name tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 tnm1~tnm0 : select tmn operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the tnm1 and tnm0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1~tnio0 : select tpn_0, tpn_1 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a compare match occurs from the compara tor a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a . when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit in the tmnc1 register . note that t he o utput l evel r equested b y t he t nio1 a nd t nio0 b its m ust b e d ifferent f rom the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odifed by c hanging t hese t wo bi ts. it i s ne cessary t o c hange t he va lues of the tnio1 and tnio0 bits only after the tmn has been switched of f. unpredictable pwm outputs will occur if the tnio1 and tnio0 bits are changed when the tm is running bit 3 tnoc : tpn_0, tpn_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode. it has no effect if the tm is in the t imer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low.
rev. 1.20 76 ????st 10? 2012 rev. 1.20 77 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bit 2 tnpol : tpn_0, tpn_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn_0 or tpn_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the t imer/counter mode. bit 1 tndpx : tmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 tncclr : select tmn counter clear condition 0: tmn comparatror p match 1: tmn comparatror a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he compact tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemen ted if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm mode. compact type tm operating modes the compact t ype tm can operate in one of three operating modes, compare match output mode, pwm mo de o r t imer/counter mo de. t he o perating m ode i s se lected u sing t he t nm1 a nd t nm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register , should be set to "00" respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch o ccurs f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich allows the counter to overfow . here both tnaf and tnpf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the tnaf interrupt request fag will not be generated.
rev. 1.20 78 ???? st 10 ? 2012 rev. 1.20 79 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when an tnaf interrupt request flag is ge nerated a fter a c ompare m atch oc curs fro m co mparator a. t he t npf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he tnio1 and tnio0 bits in the tmnc1 register . the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place. ccr? ccrp 0x3ff co?nter overflow ccr? int. fla? tn?f ccrp int. fla? tnpf ccrp > 0 co?nter cleared by ccrp val?e tm o/p pin tnon pa?se co?nter reset o?tp?t pin set to initial level low if tnoc = 0 o?tp?t to??le with tn?f fla? here tnio [1:0] = 11 to??le o?tp?t select now tnio [1:0] = 10 ?ctive hi?h o?tp?t select o?tp?t not affected by tn?f fla?. remains hi?h ?ntil reset by tnon bit tncclr = 0; tnm [1:0] = 00 tnp?u res?me stop time ccrp > 0 ccrp = 0 tn?pol o?tp?t pin reset to initial val?e o?tp?t inverts when tnpol is hi?h o?tp?t controlled by other pin - shared f?nction co?nter val?e compare match output mode C tncclr = 0 note: 1. w ith tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge
rev. 1.20 78 ????st 10? 2012 rev. 1.20 79 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver ccrp ccr? 0x3ff ccr? = 0 co?nter overflows ccrp int. fla? tnpf ccr? int. fla? tn?f ccr? > 0 co?nter cleared by ccr? val?e tm o/p pin tnon pa?se co?nter reset o?tp?t pin reset to initial val?e o?tp?t pin set to initial level low if tnoc = 0 o?tp?t to??le with tn?f fla? here tnio [1:0] = 11 to??le o?tp?t select now tnio [1:0] = 10 ?ctive hi?h o?tp?t select tnp?u res?me stop time tnpf not ?enerated no tn?f fla? ?enerated on ccr? overflow o?tp?t does not chan?e ccr? = 0 o?tp?t inverts when tnpol is hi?h tnpol tncclr = 1; tnm [1:0] = 00 o?tp?t controlled by other pin - shared f?nction o?tp?t not affected by tn?f fla? remains hi?h ?ntil reset by tnon bit co?nter val?e compare match output mode C tncclr = 1 note: 1. w ith tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1 timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function.
rev. 1.20 80 ???? st 10 ? 2012 rev. 1.20 81 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively . the pwm functio n within the tm is useful for applications which require functions such as motor control, h eating c ontrol, i llumination c ontrol e tc. b y p roviding a si gnal o f f ixed f requency b ut of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pwm m ode, t he t ncclr bi t ha s no e ffect on t he pwm operation. bot h of t he ccra a nd ccrp re gisters a re use d t o ge nerate t he pw m wave form, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register . the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ccrp ccr? co?nter val?e co?nter cleared by ccrp ccr? int. fla? tn?f ccrp int. fla? tnpf tm o/p pin tnoc = 1 tnon co?nter stop if tnon bit low co?nter reset when tnon ret?rns hi?h pwm res?mes operation time tnpol o?tp?t inverts when tnpol = 1 tm o/p pin tnoc = 0 tnp?u res?me pa?se tndpx = 0 ; tnm [1:0] = 10 o?tp?t controlled by other pin - shared f?nction pwm period set by ccrp pwm d?ty cycle set by ccr? pwm mode C tndpx = 0 note: 1. here tndpx=0 -- counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.20 80 ????st 10? 2012 rev. 1.20 81 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver ccr? ccrp co?nter val?e co?nter cleared by ccr ? ccr? int. fla? tn?f ccrp int. fla? tnpf tm o/p pin tnoc = 1 tnon co?nter stop if tnon bit low co?nter reset when tnon ret?rns hi?h pwm res?mes operation time tnpol o?tp?t inverts when tnpol = 1 tm o/p pin tnoc = 0 tnp?u res?me pa?se tndpx = 1 ; tnm [1:0] = 10 o?tp?t controlled by other pin - shared f?nction pwm period set by ccr ? pwm d?ty cycle set by ccr p pwm mode C tndpx = 1 note: 1. here tndpx = 1 -- counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation ctm, pwm mode, edge-aligned mode, t0dpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 d ? ty ccr ? if f sys = 16mhz, tm clock source is f sys /4, ccrp = 100b and ccra =128, the ctm pwm output frequency = (f sys /4) / 512 = f sys /2048 = 7.8125 khz, duty = 128/512 = 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ctm, pwm mode, edge-aligned mode, t0dpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccr ? d ? ty 128 256 384 512 640 768 896 1024 the output period is determined by the ccra register value together with the tm clock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.20 82 ???? st 10 ? 2012 rev. 1.20 83 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver standard type tm C stm the standard t ype tm contains fve operating modes, which are compare match output, t imer/ event counter , capture input, single pulse output and pwm output modes. the standard tm can also be controlled with an external input pin and can drive one or two external output pins. ctm name tm no. tm input pin tm output pin bs85b12-3 bs85c20-3 /bs85c20-5 10-bit stm 2 tck2 tp2_0 ? tp2_1 standard tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a a nd com parator p. t hese c omparators wi ll c ompare t he v alue i n t he c ounter wi th c crp a nd c cra r egisters. t he ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when thes e conditions occur , a tm interrupt s ignal w ill als o us ually be generated. the s tandard type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
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rev. 1.20 82 ????st 10? 2012 rev. 1.20 83 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver standard type tm register description overall operation of the standard tm is controlled using a series of registers. a read only register pair e xists t o st ore t he i nternal c ounter 10 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. stm register list name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm2c0 t2p ? u t2ck2 t2ck1 t2ck0 t2on t2rp2 t2rp1 t2rp0 tm2c1 t2m1 t2m0 t2io1 t2io0 t2oc t2pol t2dpx t2cclr tm2dl d7 d6 d5 d4 d3 d2 d1 d0 tm2dh d9 d8 tm2 ? l d7 d6 d5 d4 d3 d2 d1 d0 tm2 ? h d9 d8 10-bit standard tm register list tm2c0 register bit 7 6 5 4 3 2 1 0 name t2p ? u t2ck2 t2ck1 t2ck0 t2on t2rp2 t2rp1 t2rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t2pau : tm2 counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t2ck2~t2ck0 : select tm2 counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f tbc 101: undefned 110: tck2 rising edge clock 111: tck2 falling edge clock these three bits are used to select the clock source for the tm. selectin g the reserved clock input will ef fectively disable the internal counter . the external pin clock source can be chosen to be act ive on the rising or falling edge . the cl ock source f is the system c lock, wh ile f h a nd f tbc a re o ther i nternal c locks, t he d etails o f wh ich c an b e found in the oscillator section. bit 3 t2on : tm2 counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, cle aring the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit change s from high to low , the internal counter will retain its residual value until the bit returns high again.
rev. 1.20 84 ???? st 10 ? 2012 rev. 1.20 85 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t2oc bit, when the t2on bit changes from low to high. bit 2~0 t2rp2~t2rp0 : tm2 ccrp 3-bit register, compared with the tm2 counter bit 9~bit 7 comparator p match period 000: 1024 tm2 clocks 001: 128 tm2 clocks 010: 256 tm2 clocks 011: 384 tm2 clocks 100: 512 tm2 clocks 101: 640 tm2 clocks 110: 768 tm2 clocks 111: 896 tm2 clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are t hen c ompared wi th t he i nternal c ounter's h ighest t hree b its. t he r esult o f t his comparison c an be se lected t o c lear t he i nternal c ounter i f t he t 2cclr bi t i s se t t o zero. set ting t he t 2cclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value. tm2c1 register bit 7 6 5 4 3 2 1 0 name t2m1 t2m0 t2io1 t2io0 t2oc t2pol t2dpx t2cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t2m1~t2m0 : select tm2 operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the t2m1 and t2m0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 t2io1~t2io0 : select tp2_0, tp2_1 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp2_0, tp2_1 01: input capture at falling edge of tp2_0, tp2_1 10: input capture at falling/rising edge of tp2_0, tp2_1 11: input capture disabled timer/counter mode: unused
rev. 1.20 84 ????st 10? 2012 rev. 1.20 85 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t2io1 and t2io0 bits determine how the tm output pin changes state when a compare match occurs from the compara tor a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a . when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t2oc bit in the tm2c1 register . note that t he o utput l evel r equested b y t he t 2io1 a nd t 2io0 b its m ust b e d ifferent f rom the initial value setup using the t2oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t2on bit from low to high. in the pwm mode, the t2io1 and t2io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odifed by c hanging t hese t wo bi ts. it i s ne cessary t o c hange t he va lues of the t2io1 and t2io0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the t2io1 and t2io0 bits are changed when the tm is running bit 3 t2oc : tp2_0, tp2_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no ef fect if the tm is in the t imer/counter mode. in the co mpare ma tch out put mode i t de termines t he l ogic l evel of t he t m ou tput pi n before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t2pol : tp2_0, tp2_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp2_0 or tp2_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the t imer/counter mode. bit 1 t2dpx : tm1 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t2cclr : select tm1 counter clear condition 0: tm2 comparatror p match 1: tm2 comparatror a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he standard tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the t2cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemen ted if the ccrp bits are all cleared to zero. the t2cclr bit is not used in the pwm, single pulse or input capture mode.
rev. 1.20 86 ???? st 10 ? 2012 rev. 1.20 87 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver tm2dl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm2dl : tm2 counter low byte register bit 7~bit 0 tm2 10-bit counter bit 7~bit 0 tm2dh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm2dh : tm2 counter high byte register bit 1~bit 0 tm2 10-bit counter bit 9~bit 8 tm2al register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm2al : tm2 ccra low byte register bit 7~bit 0 tm2 10-bit ccra bit 7~bit 0 tm2ah registe bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm2ah : tm2 ccra high byte register bit 1~bit 0 tm2 10-bit ccra bit 9~bit 8
rev. 1.20 86 ????st 10? 2012 rev. 1.20 87 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver standard type tm operating modes the st andard t ype t m ca n operat e i n one of five operat ing m odes, com pare ma tch out put mode, pwm mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich a llows the c ounter t o ove rfow. he re bot h t naf a nd t npf i nterrupt re quest fa gs for com parator a a nd comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr i s h igh n o t npf i nterrupt r equest fa g wi ll b e g enerated. i n t he c ompare ma tch ou tput mode, the ccra can not be set to 0. ccr? ccrp 0x3ff co?nter overflow ccr? int. fla? tn?f ccrp int. fla? tnpf ccrp > 0 co?nter cleared by ccrp val?e tm o/p pin tnon pa?se co?nter reset o?tp?t pin set to initial level low if tnoc = 0 o?tp?t to??le with tn?f fla? here tnio [1:0] = 11 to??le o?tp?t select now tnio [1:0] = 10 ?ctive hi?h o?tp?t select o?tp?t not affected by tn?f fla?. remains hi?h ?ntil reset by tnon bit tncclr = 0; tnm [1:0] = 00 tnp?u res?me stop time ccrp > 0 ccrp = 0 tn?pol o?tp?t pin reset to initial val?e o?tp?t inverts when tnpol is hi?h o?tp?t controlled by other pin - shared f?nction co?nter val?e compare match output mode C tncclr = 0 note: 1. w ith tncclr=0 a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to itsinitial state by a tnon bit rising edge
rev. 1.20 88 ???? st 10 ? 2012 rev. 1.20 89 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is ge nerated a fter a c ompare m atch oc curs fro m co mparator a. t he t npf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he tnio1 and tnio0 bits in the tmnc1 register . the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place. timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. ccrp ccr? 0x3ff ccr? = 0 co?nter overflows ccrp int. fla? tnpf ccr? int. fla? tn?f ccr? > 0 co?nter cleared by ccr? val?e tm o/p pin tnon pa?se co?nter reset o?tp?t pin reset to initial val?e o?tp?t pin set to initial level low if tnoc = 0 o?tp?t to??le with tn?f fla? here tnio [1:0] = 11 to??le o?tp?t select now tnio [1:0] = 10 ?ctive hi?h o?tp?t select tnp?u res?me stop time tnpf not ?enerated no tn?f fla? ?enerated on ccr? overflow o?tp?t does not chan?e ccr? = 0 o?tp?t inverts when tnpol is hi?h tnpol tncclr = 1; tnm [1:0] = 00 o?tp?t controlled by other pin - shared f?nction o?tp?t not affected by tn?f fla? remains hi?h ?ntil reset by tnon bit co?nter val?e compare match output mode C tncclr = 1 note: 1. w ith tncclr=1 a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. a tnpf fag is not generated when tncclr=1
rev. 1.20 88 ????st 10? 2012 rev. 1.20 89 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively . the pwm functio n within the tm is useful for applications which require functions such as motor control, h eating c ontrol, i llumination c ontrol e tc. b y p roviding a si gnal o f f ixed f requency b ut of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pwm m ode, t he t ncclr bi t ha s no e ffect on t he pwm operation. bot h of t he ccra a nd ccrp re gisters a re use d t o ge nerate t he pw m wave form, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register . the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. stm, pwm mode, edge-aligned mode, tndpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 d ? ty ccr ? if f sys = 16mhz, tm clock source is f sys /4, ccrp = 100b and ccra =128, the stm pwm output frequency = (f sys /4) / 512 = f sys /2048 = 7.8125 khz, duty = 128/512 = 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. stm, pwm mode, edge-aligned mode, tndpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccr ? d ? ty 128 256 384 512 640 768 896 1024 the pw m o utput p eriod i s d etermined b y t he c cra r egister v alue t ogether wi th t he t m c lock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.20 90 ???? st 10 ? 2012 rev. 1.20 91 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver ccrp ccr? co?nter val?e co?nter cleared by ccrp ccr? int. fla? tn?f ccrp int. fla? tnpf tm o/p pin tnoc = 1 tnon co?nter stop if tnon bit low co?nter reset when tnon ret?rns hi?h pwm res?mes operation time tnpol o?tp?t inverts when tnpol = 1 tm o/p pin tnoc = 0 tnp?u res?me pa?se tndpx = 0 ; tnm [1:0] = 10 o?tp?t controlled by other pin - shared f?nction pwm period set by ccrp pwm d?ty cycle set by ccr? pwm mode C tndpx = 0 note: 1. here tndpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.20 90 ????st 10? 2012 rev. 1.20 91 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver ccr? ccrp co?nter val?e co?nter cleared by ccr ? ccr? int. fla? tn?f ccrp int. fla? tnpf tm o/p pin tnoc = 1 tnon co?nter stop if tnon bit low co?nter reset when tnon ret?rns hi?h pwm res?mes operation time tnpol o?tp?t inverts when tnpol = 1 tm o/p pin tnoc = 0 tnp?u res?me pa?se tndpx = 1 ; tnm [1:0] = 10 o?tp?t controlled by other pin - shared f?nction pwm period set by ccr ? pwm d?ty cycle set by ccr p pwm mode C tndpx = 1 note: 1. here tndpx=1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation single pulse mode to se lect t his mode , bit s t nm1 and t nm0 i n t he t mnc1 regi ster should be se t t o 10 respe ctively and also the tnio1 and tnio0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output lead ing edge is a low to high transition of the tnon bit, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a.
rev. 1.20 92 ???? st 10 ? 2012 rev. 1.20 93 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver

? ? ? ? ? ?? ? ? ?? single pulse generation however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tm interrupt. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr and tndpx bits are not used in this mode. ccr? ccrp ccrp int . fla? tnpf ccr? int . fla? tn?f tm o/p pin tnoc = 1 tnon p?lse width set by ccr? tnio 1 ? tnio0 = 11 no ccrp interr?pt ?enerated co?nter stops by software co?nter reset when tnon ret?rns hi?h time tnpol o?tp?t inverts when tnpol = 1 tm o/p pin tnoc = 0 tnp?u res?me pa?se software tri??er tcn pin cleared by ccr? match tckn pin tri??er ??to. set by tckn pin software clear software tri??er software tri??er tnm [1:0] = 10; tnio [1:0] = 11 co?nter val?e co?nter stopped by ccr? tnio 1 ? tnio0 = 11 sin?le p?lse o?tp?t tnio 1 ? tnio0 = 00 o?tp?t inactive software tri??er single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse mode, tnio [1:0] must be set to "11" and can not be changed.
rev. 1.20 92 ????st 10? 2012 rev. 1.20 93 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver capture input mode to s elect this mode bits tnm1 and tnm0 in the tm nc1 regis ter s hould be s et to 01 res pectively. this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and can therefore be used for applic ations such as pulse width measurements. the external signal is supplied on the tpn_0 or tpn_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnio1 and tnio0 bits in the tm nc1 regis ter. the counter is s tarted w hen the tno n bit changes from low to high which is initiated using the application program. when t he r equired e dge t ransition a ppears o n t he t pn_0 o r t pn_1 p in, t he p resent v alue i n t he counter will be latched into the ccra registers and a tm interrupt ge nerated. irrespective of what events occur on the tpn_0 or tpn_1 pin the counter will continu e to free run until the tnon bit c hanges from hi gh t o l ow. when a ccrp c ompare m atch oc curs, t he c ounter wi ll re set ba ck to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a tm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnio1 and tnio0 bits can select the active trigger edge on the tpn_0 or tpn_1 pin to be a ris ing edge, falling edge or both edge types . if the tnio 1 and tnio 0 bits are both s et high, then no capture operation will take place irrespective of what happens on the tpn_0 or tpn_1 pin, however it must be noted that the counter will continue to run. as the tpn_0 or tpn_1 pin is pin shared with other functions, care must be taken if the tm is in the input capture mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr and tndpx bits are not used in this mode. ccrp co?nter val?e co?nter overflow ccrp int . fla? tnpf ccr? int . fla? tn?f tnon pa?se co?nter reset tnp?u res?me stop time yy xx ccr? val?e xx tm capt?re pin tpn yy tnio [1:0] val?e 00 - risin? ed?e 01 - fallin? ed?e 11 - disable capt?re ?ctive ed?e ?ctive ed?e xx 10 - both ed?es ?ctive ed?e yy tnm [1:0] = 01 time xx yy 00 - risin? ed?e 01 - fallin? ed?e 11 - disable capt?re xx 10 - both ed?es yy tnm [1:0] = 01 capture input mode note: 1.. tnm [1:0] = 01 and active edge set by the tnio [1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function -- tnoc and tnpol bits are not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.20 94 ???? st 10 ? 2012 rev. 1.20 95 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver enhanced type tm C etm the enhanced t ype tm contains fve operating modes, which are compare match output, t imer/ event counter , capture input, single pulse output and pwm output modes. the enhanced tm can also be controlled with an external input pin and can drive three or four external output pins. ctm name tm no. tm input pin tm output pin bs85b12-3 10-bit etm 1 tck1 tp1 ?? tp1b_0 ? tp1b_1 ? tp1b_2 bs85c20-3 /bs85c20-5 10-bit etm 1 tck1 tp1 ?? tp1b_0 ? tp1b_1 ? tp1b_2 enhanced tm operation at its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock s ource. there are three internal comparators w ith the names, comparator a , comparator b and comparator p . these comparators will compare the value in the counter with the ccra, ccrb and ccrp registers. the ccrp comparator is 3-bits wide whose value is compared with the highest 3-bits in the counter while ccra and ccrb are 10-bits wide and therefore compared with all counter bits. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the enhanced type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control output pins. all operating setup conditions are selected using relevant internal registers.
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rev. 1.20 94 ????st 10? 2012 rev. 1.20 95 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver enhanced type tm register description overall operation of the enhanced tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrb value. the remaining three registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm1c0 t1p ? u t1ck2 t1ck1 t1ck0 t1on t1rp2 t1rp1 t1rp0 tm1c1 t1 ? m1 t1 ? m0 t1 ? io1 t1 ? io0 t1 ? oc t1 ? pol t1cdn t1cclr tm1c2 t1bm1 t1bm0 t1bio1 t1bio0 t1boc t1bpol t1pwm1 t1pwm0 tm1dl d7 d6 d5 d4 d3 d2 d1 d0 tm1dh d9 d8 tm1 ? l d7 d6 d5 d4 d3 d2 d1 d0 tm1 ? h d9 d8 tm1bl d7 d6 d5 d4 d3 d2 d1 d0 tm1bh d9 d8 10-bit enhanced tm register list 10-bit enhanced tm register list ? tm1c0 register C 10-bit etm bit 7 6 5 4 3 2 1 0 name t1p ? u t1ck2 t1ck1 t1ck0 t1on t1rp2 t1rp1 t1rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t1pau : tm1 counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t1ck2~t1ck0 : select tm1 counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f tbc 101: undefned 110: tck1 rising edge clock 111: tck1 falling edge clock these three bits are used to select the clock source for the tm. selectin g the reserved clock input will ef fectively disable the internal counter . the external pin clock source can be chosen to be act ive on the rising or falling edge . the clock source f is the system c lock, wh ile f h a nd f tbc a re o ther i nternal c locks, t he d etails o f wh ich c an b e found in the oscillator section.
rev. 1.20 96 ???? st 10 ? 2012 rev. 1.20 97 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bit 3 t1on : tm1 counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, cle aring the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit change s from high to low , the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t1oc bit, when the t1on bit changes from low to high. bit 2~0 t1rp2~t1rp0 : tm1 3-bit register, compared with the tm1 counter bit 9~bit 7 comparator p match period 000: 1024 tm1 clocks 001: 128 tm1 clocks 010: 256 tm1 clocks 011: 384 tm1 clocks 100: 512 tm1 clocks 101: 640 tm1 clocks 110: 768 tm1 clocks 111: 896 tm1 clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are t hen c ompared wi th t he i nternal c ounter's h ighest t hree b its. t he r esult o f t his comparison c an be se lected t o c lear t he i nternal c ounter i f t he t 1cclr bi t i s se t t o zero. set ting t he t 1cclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value. ? tm1c1 register C 10-bit etm bit 7 6 5 4 3 2 1 0 name t1 ? m1 t1 ? m0 t1 ? io1 t1 ? io0 t1 ? oc t1 ? pol t1cdn t1cclr r/w r/w r/w r/w r/w r/w r/w r r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1am1~t1am0 : select tm1 ccra operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm shoul d be switched of f before any changes are made to the t1am1 and t1am0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 t1aio1~t1aio0 : select tp1a output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output mode/ single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output
rev. 1.20 96 ????st 10? 2012 rev. 1.20 97 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver capture input mode 00: input capture at rising edge of tp1a 01: input capture at falling edge of tp1a 10: input capture at falling/rising edge of tp1a 11: input capture disabled timer/counter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1aoc bit in the tm1c1 register . note that the output level requested by the t1aio1 and t1aio0 bits must be dif ferent from the initial value setup using the t1aoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the t1aio1 and t1aio0 b its o nly a fter t he t m h as b een swi tched o ff. un predictable pw m o utputs will occur if the t1aio1 and t1aio0 bits are changed when the tm is running bit 3 t1aoc : tp1a output control bit compare match output mode 0: initial low 1: initial high mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the t imer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1apol : tp1a output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1a output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the tm is in the t imer/counter mode. bit 1 t1cdn : tm1 counter count up or down fag 0: count up 1: count down bit 0 t1cclr : select tm1 counter clear condition 0: tm1 comparator p match 1: tm1 comparator a match this b it i s u sed t o se lect t he m ethod wh ich c lears t he c ounter. r emember t hat t he enhanced tm contains three comparators, comparator a, comparator b and comparator p, but only comparator a or comparator pan be selected to clear the internal counter . w ith the t1cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the single pulse or input capture mode.
rev. 1.20 98 ???? st 10 ? 2012 rev. 1.20 99 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver ? tm1c2 register C 10-bit etm bit 7 6 5 4 3 2 1 0 name t1bm1 t1bm0 t1bio1 t1bio0 t1boc t1bpol t1pwm1 t1pwm0 r/w r/w r/w r/w r/w r/w r/w r r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1bm1~t1bm0 : select tm1 ccrb operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the t m sh ould b e swi tched o ff b efore a ny c hanges a re m ade t o t he t 1bm1 a nd t1bm0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 t1bio1~t1bio0 : select tp1b_0, tp1b_1, tp1b_2 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1b_0, tp1b_1, tp1b_2 01: input capture at falling edge of tp1b_0, tp1b_1, tp1b_2 10: input capture at falling/rising edge of tp1b_0, tp1b_1, tp1b_2 11: input capture disabled timer/counter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1bio1 and t1bio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1boc bit in the tm1c2 register . note that the output level re quested by t he t 1bio1 a nd t 1bio0 bi ts m ust be di fferent from t he i nitial value setup using the t1boc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in t he pwm mode , t he t 1bio1 a nd t 1bio0 bi ts de termine how t he t m out put pi n changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the t1bio1 and t1bio0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the t1bio1 and t1bio0 bits are changed when the tm is running
rev. 1.20 98 ????st 10? 2012 rev. 1.20 99 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bit 3 t1boc : tp1b_0, tp1b_1, tp1b_2 output control bit compare match output mode 0: initial low 1: initial high mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no ef fect if the tm is in the t imer/counter mode. in the co mpare ma tch out put mode i t de termines t he l ogic l evel of t he t m ou tput pi n before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1bpol : tp1b_0, tp1b_1, tb1b_2 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1b_0, tp1b_1, tp1b_2 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the t imer/counter mode. bit 1~0 t1pwm1~t1pwm0 : select pwm mode 00: edge aligned 01: centre aligned, compare match on count up 10: centre aligned, compare match on count down 11: centre aligned, compare match on count up or down ? tm1dl register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm1dl : tm1 counter low byte register bit 7~bit 0 tm1 10-bit counter bit 7~bit 0 ? tm1dh register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm1dh : tm1 counter high byte register bit 1~bit 0 tm1 10-bit counter bit 9~bit 8 ? tm1al register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1al : tm1 low byte register bit 7~bit 0 tm1 10-bit ccra bit 7~bit 0
rev. 1.20 100 ???? st 10 ? 2012 rev. 1.20 101 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver ? tm1ah register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm1ah : tm1 high byte register bit 1~bit 0 tm1 10-bit ccra bit 9~bit 8 ? tm1bl register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 tm1bl : tm1 low byte register bit 7~bit 0 tm1 10-bit ccrb bit 7~bit 0 ? tm1bh register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm1bh : tm1 high byte register bit 1~bit 0 tm1 10-bit ccrb bit 9 ~ bit 8 enhanced type tm operating modes the enhanced t ype tm can operat e in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the tnam1 and tnam0 bits in the tmnc1, and the tnbm1 and tnbm0 bits in the tmnc2 register. etm operating mode ccra compare match output mode ccra timer/counter mode ccra pwm output mode ccra single pulse output mode ccra input capture mode ccrb compare match o ? tp ? t mode ccrb timer/co ? nter mode ccrb pwm o ? tp ? t mode ccrb sin ? le p ? lse o ? tp ? t mode ccrb inp ? t capt ? re mode "": permitted; "" : not permitted
rev. 1.20 100 ????st 10? 2012 rev. 1.20 101 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver compare output mode to select this mode, bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1/tmnc2 registers should be all clear ed to zero. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p , the other is when the ccrp bits are all zero which allows the counter to overfow. here both the tnaf and tnpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. ccr? ccrp 0x3ff co ? nter overflow ccr? int. fla ? tn ?f ccrp int. fla ? tnpf ccrp > 0 co ? nter cleared by ccrp val ? e tpn ? o/p pin tnon bit pa ? se co ? nter reset o? tp ? t pin reset to initial val ? e o ? tp ? t pin set to initial level low if tn ? oc = 0 o ? tp ? t to ?? le with tn ?f fla ? here tn ? io1 ? tn ? io0 = 11 to ?? le o ? tp? t select now tn ? io1 ? tn ? io0 = 10 ? ctive hi ? h o ? tp? t select tncclr = 0; tn ? m1 ? tn? m0 = 00 tnp ?u bit res ? me stop ccrp > 0 ccrp = 0 tn ? pol bit o ? tp ? t inverts when tn ? pol is hi ?h o ? tp ? t controlled by other pin - shared f ? nction o ? tp ? t not affected by tn ? f fla ? . remains hi ?h ? ntil reset by tnon bit co ? nter val ? e time ccr? ccrp 0x3ff co ? nter overflow ccr? int. fla ? tn ?f ccrp int. fla ? tnpf ccrp > 0 co ? nter cleared by ccrp val ? e tpn ? o/p pin tnon bit pa ? se co ? nter reset o? tp ? t pin reset to initial val ? e o ? tp ? t pin set to initial level low if tn ? oc = 0 o ? tp ? t to ?? le with tn ?f fla ? here tn ? io1 ? tn ? io0 = 11 to ?? le o ? tp? t select now tn ? io1 ? tn ? io0 = 10 ? ctive hi ? h o ? tp? t select tncclr = 0; tn ? m1 ? tn? m0 = 00 tnp ?u bit res ? me stop ccrp > 0 ccrp = 0 tn ? pol bit o ? tp ? t inverts when tn ? pol is hi ?h o ? tp ? t controlled by other pin - shared f ? nction o ? tp ? t not affected by tn ? f fla ? . remains hi ?h ? ntil reset by tnon bit co ? nter val ? e time etm ccra compare match output mode C tncclr = 0 note: 1. w ith tncclr=0 a comparator p match will clear the counter 2. the tpna output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge
rev. 1.20 102 ???? st 10 ? 2012 rev. 1.20 103 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. t he t m out put pi n c ondition howe ver onl y c hanges st ate whe n a n t naf or t nbf i nterrupt request fag is generated after a compare match occurs from comparator a or comparator b. the tnpf interrupt request flag, generated from a compare match from comparator p , will have no effect on the tm output pin. the way in which the tm output pin changes state is determined by the condition of the tnaio1 and tnaio0 bits in the tmnc1 register for etm ccra, and the tnbio1 and tnbio0 bits in the tmnc2 register for etm ccrb. the tm output pin can be selected using the tnaio1, tnaio0 bits (for the tpna pin) and tnbio1, tnbio0 bits (for the tpnb_0, tpnb_1 or tpnb_2 pins) to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a or a compare match occurs from comparator b. the initial condition of t he t m out put pi n, whi ch i s se tup a fter t he t non bi t c hanges from l ow t o hi gh, i s se tup usi ng the t naoc o r t nboc b it f or t pna o r t pnb_0, t pnb_1, t pnb_2 o utput p ins. no te t hat i f t he tnaio1,tnaio0 and tnbio1, tnbio0 bits are zero then no pin change will take place. ccrb ccrp 0x3ff co ? nter overflow ccrb int. fla ? tnb? f ccrp int. fla ? tnpf ccrp > 0 co ? nter cleared by ccrp val ? e tpnb o/p pin tnon bit pa ? se co ? nter reset o ? tp ? t pin set to initial level low if tnboc = 0 o ? tp ? t to ?? le with tnbf fla ? here tnbio1 ? tnbio0 = 11 to ?? le o ? tp? t select now tnbio1 ? tnbio0 = 10 ? ctive hi ? h o ? tp? t select tncclr = 0; tnbm1 ? tnbm0 = 00 tnp ?u bit res ? me stop ccrp > 0 ccrp = 0 tnbpol bit o? tp ? t pin reset to initial val ? e o ? tp ? t inverts when tnbpol is hi ?h o ? tp ? t controlled by other pin - shared f ? nction o ? tp ? t not affected by tnbf fla ? . remains hi ?h ? ntil reset by tnon bit co ? nter val ? e time ccrb ccrp 0x3ff co ? nter overflow ccrb int. fla ? tnb? f ccrp int. fla ? tnpf ccrp > 0 co ? nter cleared by ccrp val ? e tpnb o/p pin tnon bit pa ? se co ? nter reset o ? tp ? t pin set to initial level low if tnboc = 0 o ? tp ? t to ?? le with tnbf fla ? here tnbio1 ? tnbio0 = 11 to ?? le o ? tp? t select now tnbio1 ? tnbio0 = 10 ? ctive hi ? h o ? tp? t select tncclr = 0; tnbm1 ? tnbm0 = 00 tnp ?u bit res ? me stop ccrp > 0 ccrp = 0 tnbpol bit o? tp ? t pin reset to initial val ? e o ? tp ? t inverts when tnbpol is hi ?h o ? tp ? t controlled by other pin - shared f ? nction o ? tp ? t not affected by tnbf fla ? . remains hi ?h ? ntil reset by tnon bit co ? nter val ? e time etm ccrb compare match output mode C tncclr = 0 note: 1. w ith tncclr=0 a comparator p match will clear the counter 2. the tpnb output pin is controlled only by the tnbf fag 3. the output pin is reset to its initial state by a tnon bit rising edge
rev. 1.20 102 ????st 10? 2012 rev. 1.20 103 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver ccr? ccrp 0x3ff co ? nter overflow ccr? int. fla ? tn ?f ccrp int. fla ? tnpf ccrp > 0 co ? nter cleared by ccrp val ? e tpn ? o/p pin tnon bit pa ? se co ? nter reset o? tp ? t pin reset to initial val ? e o ? tp ? t pin set to initial level low if tn ? oc = 0 o ? tp ? t to ?? le with tn ?f fla ? here tn ? io1 ? tn ? io0 = 11 to ?? le o ? tp? t select now tn ? io1 ? tn ? io0 = 10 ? ctive hi ? h o ? tp? t select tncclr = 0; tn ? m1 ? tn? m0 = 00 tnp ?u bit res ? me stop ccrp > 0 ccrp = 0 tn ? pol bit o ? tp ? t inverts when tn ? pol is hi ?h o ? tp ? t controlled by other pin - shared f ? nction o ? tp ? t not affected by tn ? f fla ? . remains hi ?h ? ntil reset by tnon bit co ? nter val ? e time ccr? ccrp 0x3ff co ? nter overflow ccr? int. fla ? tn ?f ccrp int. fla ? tnpf ccrp > 0 co ? nter cleared by ccrp val ? e tpn ? o/p pin tnon bit pa ? se co ? nter reset o? tp ? t pin reset to initial val ? e o ? tp ? t pin set to initial level low if tn ? oc = 0 o ? tp ? t to ?? le with tn ?f fla ? here tn ? io1 ? tn ? io0 = 11 to ?? le o ? tp? t select now tn ? io1 ? tn ? io0 = 10 ? ctive hi ? h o ? tp? t select tncclr = 0; tn ? m1 ? tn? m0 = 00 tnp ?u bit res ? me stop ccrp > 0 ccrp = 0 tn ? pol bit o ? tp ? t inverts when tn ? pol is hi ?h o ? tp ? t controlled by other pin - shared f ? nction o ? tp ? t not affected by tn ? f fla ? . remains hi ?h ? ntil reset by tnon bit co ? nter val ? e time etm ccra compare match output mode C tncclr = 1 note: 1. w ith tncclr=1 a comparator a match will clear the counter 2. the tpna output pin is controlled only by the tnaf fag 3. the tpna output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1
rev. 1.20 104 ???? st 10 ? 2012 rev. 1.20 105 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver ccrb ccrp 0x3ff co ? nter overflow ccrb int. fla ? tnb? f ccrp int. fla ? tnpf ccrp > 0 co ? nter cleared by ccrp val ? e tpnb o/p pin tnon bit pa ? se co ? nter reset o ? tp ? t pin set to initial level low if tnboc = 0 o ? tp ? t to ?? le with tnbf fla ? here tnbio1 ? tnbio0 = 11 to ?? le o ? tp? t select now tnbio1 ? tnbio0 = 10 ? ctive hi ? h o ? tp? t select tncclr = 0; tnbm1 ? tnbm0 = 00 tnp ?u bit res ? me stop ccrp > 0 ccrp = 0 tnbpol bit o? tp ? t pin reset to initial val ? e o ? tp ? t inverts when tnbpol is hi ?h o ? tp ? t controlled by other pin - shared f ? nction o ? tp ? t not affected by tnbf fla ? . remains hi ?h ? ntil reset by tnon bit co ? nter val ? e time ccrb ccrp 0x3ff co ? nter overflow ccrb int. fla ? tnb? f ccrp int. fla ? tnpf ccrp > 0 co ? nter cleared by ccrp val ? e tpnb o/p pin tnon bit pa ? se co ? nter reset o ? tp ? t pin set to initial level low if tnboc = 0 o ? tp ? t to ?? le with tnbf fla ? here tnbio1 ? tnbio0 = 11 to ?? le o ? tp? t select now tnbio1 ? tnbio0 = 10 ? ctive hi ? h o ? tp? t select tncclr = 0; tnbm1 ? tnbm0 = 00 tnp ?u bit res ? me stop ccrp > 0 ccrp = 0 tnbpol bit o? tp ? t pin reset to initial val ? e o ? tp ? t inverts when tnbpol is hi ?h o ? tp ? t controlled by other pin - shared f ? nction o ? tp ? t not affected by tnbf fla ? . remains hi ?h ? ntil reset by tnon bit co ? nter val ? e time etm ccrb compare match output mode C tncclr = 1 note: 1. w ith tncclr=1 a comparator a match will clear the counter 2. the tpnb output pin is controlled only by the tnbf fag 3. the tpnb output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1
rev. 1.20 104 ????st 10? 2012 rev. 1.20 105 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver timer/counter mode to select this mode, bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 register should all be set high. the t imer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 should be set to 10 respectively and also the tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 10 respectively. the p wm function w ithin the tm is us eful for applications w hich require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely fexible. in the pwm mode, the tncclr bit is used to determine in which way the pwm period is controlled. w ith the tncclr bit set high, the pwm period can be fnely controlled using the ccra registers. in this case the ccrb registers are used to set the pwm duty value (for tpnb output pins). the ccrp bits are not used and tpna output pin is not used. the pwm output can only be generated on the tpnb output pins. w ith the tncclr bit cleared to zero, the pwm period is set using one of the eight values of the three ccrp bits, in multiples of 128. now both ccra and ccrb registers can be used to setup dif ferent duty cycle values to provide dual pwm outputs on their relative tpna and tpnb pins. the tnpwm1 and tnpwm0 bits determine the pwm alignment type, which can be either edge or centre type. in edge alignment, the leading edge of the pwm signals will all be generated concurrently when the counter is reset to zero. w ith all power currents switching on at the same time, this may give rise to problems in higher power applications. in centre alignment the centre of the pwm active signals will occur sequentially , thus reducing the level of simultaneous power switching currents. interrupt fags, one for each of the ccra, ccrb and ccrp , will be generated when a compare match occurs from either the comparator a, comparator b or comparator p . the tnaoc and tnboc bits in the tmnc1 and tmnc2 register are used to select the required polarity of the pwm waveform while the two tnaio1, tnaio0 and tnbio1, tnbio0 bits pairs are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnapol and tnbpol bit are used to reverse the polarity of the pwm output waveform.
rev. 1.20 106 ???? st 10 ? 2012 rev. 1.20 107 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver etm, pwm mode, edge-aligned mode, tncclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 ? d ? ty ccr ? b d ? ty ccrb if f sys = 16mhz, tm clock source select f sys /4, ccrp = 100b, ccra = 128 and ccrb = 256, the tp1a pwm output frequency = (f sys /4)/512 = f sys /2048 = 7.8125khz, duty = 128/512 = 25%. the tp1b_n pwm output frequency = (f sys /4)/512 = f sys /2048 = 7.8125khz, duty = 256/512 = 50% . if the duty value defned by ccra or ccrb register is equal to or greater than the period value, then the pwm output duty is 100%. etm, pwm mode, edge-aligned mode, tncclr=1 ccra 1 2 3 511 512 1021 1022 1023 period 1 2 3 511 512 1021 1022 1023 b d ? ty ccrb etm, pwm mode, center-aligned mode, tncclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 256 512 768 1024 1280 1536 1792 2046 ? d ? ty (ccr ? 2)-1 b d ? ty (ccrb2)-1 etm, pwm mode, center-aligned mode, tncclr=1 ccra 1 2 3 511 512 1021 1022 1023 period 2 4 6 1022 1024 2042 2044 2046 b d ? ty (ccrb2)-1
rev. 1.20 106 ????st 10? 2012 rev. 1.20 107 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver ccrp ccr? co?nter val?e co?nter cleared by ccrp ccr? int. fla? tn?f ccrp int. fla? tnpf tpn? pin tn?oc = 1 tnon bit d?ty cycle set by ccr? pwm period set by ccrp tn?io1? tn?io0 = 10 pwm o?tp?t tn?io1? tn?io0 = 00 o?tp?t inactive tn?io1? tn?io0 = 10 interr?pt still ?enerated here tn?io1? tn?io0 = 00 o?tp?t is inactive pwm r?ns internally tn?io1? tn?io0 = 10 res?me pwm o?tp?t time tncclr = 0 ; mode bits tn?(b)m1? tn?(b)m0 = 10 tnpwm1/tnpwm0 = 00 tn?pol bit o?tp?t inverts when tn?pol = 1 tpnb pin tnboc = 0 tnp?u bit res?me pa?se ccrb ccrb int. fla? tnbf tpnb pin tnboc = 1 d?ty cycle set by ccrb pwm res?mes operation o?tp?t controlled by other pin - shared f?nction co?nter stops if tnon bit low co?nter reset when tnon ret?rns hi?h etm pwm mode C edge aligned note: 1. here tncclr=0 therefore ccrp clears counter and determines the pwm period 2. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0]) = 00 or 01 3. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty
rev. 1.20 108 ???? st 10 ? 2012 rev. 1.20 109 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver ccr? co?nter val?e co?nter cleared by ccr? ccr? int. fla? tn?f tnon bit pwm period set by ccr? tnbpol bit tpnb pin tnboc = 0 tnp?u bit res?me pa?se ccrb ccrb int. fla? tnbf tpnb pin tnboc = 1 d?ty cycle set by ccrb o?tp?t inverts when tnbpol = 1 tncclr = 1 ; mode bits tn?(b)m1? tn?(b)m0 = 10 tnpwm1/tnpwm0 = 00 pwm res?mes operation o?tp?t controlled by other pin - shared f?nction time co?nter stops if tnon bit low co?nter reset when tnon ret?rns hi?h etm pwm mode C edge aligned note: 1. here tncclr=1 therefore ccra clears the counter and determines the pwm period 2. the internal pwm function continues running even when tnbio [1:0] = 00 or 01 3. the ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 4. here the tm pin control register should not enable the tpna pin as a tm output pin.
rev. 1.20 108 ????st 10? 2012 rev. 1.20 109 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver ccrp ccr? ccr? int. fla? tn?f ccrp int. fla? tnpf tpn? pin tn?oc = 1 tnon bit d?ty cycle set by ccr? pwm period set by ccrp tn?io1? tn?io0 = 00 o?tp?t inactive co?nter stops if tnon bit low co?nter reset when tnon ret?rns hi?h tn?pol bit o?tp?t inverts when tn?pol = 1 tpnb pin tnboc = 0 tnp?u bit res?me pa?se ccrb ccrb int. fla? tnbf tpnb pin tnboc = 1 d?ty cycle set by ccrb tn?io1? tn?io0 = 10 pwm o?tp?t tn?io1? tn?io0 = 10 pwm o?tp?t co?nter val?e tncclr = 0; mode bits tn?(b)m1? tn?(b)m0 = 10 tnpwm1/tnpwm0 = 11 time pwm res?mes operation o?tp?t controlled by other pin - shared f?nction etm pwm mode C centre aligned note: 1. here tncclr=0 therefore ccrp clears the counter and determines the pwm period 2. tnpwm [1:0] =11 therefore the pwm is centre aligned 3. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0]) = 00 or 01 4. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value
rev. 1.20 110 ???? st 10 ? 2012 rev. 1.20 111 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver ccr? ccr? int. fla? tn?f tnon bit pwm period set by ccr? time tnbpol bit o?tp?t inverts when tnbpol = 1 tpnb pin tnboc = 0 tnp?u bit res?me pa?se ccrb ccrb int. fla? tnbf tpnb pin tnboc = 1 d?ty cycle set by ccrb co?nter val?e tncclr = 1; mode bits tn?(b)m1? tn?(b)m0 = 10 tnpwm1/tnpwm0 = 11 pwm res?mes operation o?tp?t controlled by other pin - shared f?nction co?nter stops if tnon bit low co?nter reset when tnon ret?rns hi?h etm pwm mode C centre aligned note: 1. here tncclr=1 therefore ccra clears the counter and determines the pwm period. 2. tnpwm [1:0] =11 therefore the pwm is centre aligned. 3. the internal pwm function continues running even when tnbio [1:0] = 00 or 01. 4. ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty. 5. ccrp will generate an interrupt request when the counter decrements to its zero value.
rev. 1.20 110 ????st 10? 2012 rev. 1.20 111 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver single pulse output mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 should be set to 10 respectively and also the corresponding tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse tpna output leading edge is a low to high transition of the tnon bit, which can be implemented using the application program. the trigger for the pulse tpnb output leading edge i s a c ompare m atch fr om c omparator b , wh ich c an b e i mplemented u sing t he a pplication program. howe ver i n t he si ngle pul se mod e, t he t non bi t c an a lso be m ade t o a utomatically change from low to high using the external tckn pin, whi ch will in turn init iate the singl e pulse output of tpna. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge of tpna will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge of tpna and tpnb will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge of tpna and tpnb. in this way the ccra value can be u sed t o c ontrol t he p ulse wi dth o f t pna. t he c cra-ccrb v alue c an b e u sed t o c ontrol t he pulse widt h of t pnb. a c ompare m atch from com parator a a nd com parator b wil l a lso ge nerate tm inter rupts. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr bit is also not used.

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? ? - ? ?? ? ?? ? ? ? ? ? ? single pulse generation
rev. 1.20 112 ???? st 10 ? 2012 rev. 1.20 113 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver ccr? ccrb co?nter val?e co?nter stopped by ccr? ccrb int. fla? tnbf ccr? int. fla? tn?f tpn? pin tn?oc = 1 tnon bit tn?io1? tn?io0 and tnbio1? tnbio0 = 11 sin?le p?lse o?tp?t tn?io1? tn?io0 and tnbio1? tnbio0 = 00 o?tp?t inactive tn?io1? tn?io0 and tnbio1? tnbio0 = 11 here tn?io1? tn?io0 and tnbio1? tnbio0 = 00 o?tp?t forced to inactive level b?t co?nter keeps r?nnin? internally tn?io1? tn?io0 and tnbio1? tnbio0 = 11 res?me sin?le p?lse o?tp?t co?nter stops by software co?nter reset when tnon ret?rns hi?h time tn?pol ? tnbpol bit o?tp?t inverts when tn?pol = 1 tpn? pin tn?oc = 0 tnp?u bit res?me pa?se software tri??er tckn pin cleared by ccr? match tckn pin tri??er ??to. set by tckn pin software clear software tri??er software tri??er tn?m1? tn?m0 and tnbm1? tnbm0 = 10; tn?io1? tn?io0 and tnbio1? tnbio0 = 11 tpnb pin tnboc = 1 p?lse width set by ccr? tpnb pin tnboc = 0 p?lse width set by ccr? - ccrb o?tp?t inverts when tnbpol = 1 etm C single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse mode, tnaio [1:0] and tnbio [1:0] must be set to "1 1" and can not be changed.
rev. 1.20 112 ????st 10? 2012 rev. 1.20 113 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver capture input mode to select this mode bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 registers should be set to 01 respectively . this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tpna and tpnb_0, tpnb_1, tpnb_2 pins, whose a ctive e dge c an b e e ither a r ising e dge, a f alling e dge o r b oth r ising a nd f alling e dges; t he active edge transition type is selecte d using the tnaio1, tnaio0 and tnbio1, tnbio0 bits in the tmnc1 and tmnc2 registers. the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpna and tpnb_0, tpnb_1, tpnb_2 pins the present value in the counter will be latched into the ccra and ccrb registers and a tm interrupt generated. irres pective of w hat events occur on the tp na and tp nb_0, tp nb_1, tp nb_2 pins the c ounter wi ll c ontinue t o fre e run unt il t he t non bi t c hanges from hi gh t o l ow. w hen a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to c ontrol t he m aximum c ounter va lue. w hen a c crp c ompare m atch oc curs fr om co mparator p , a tm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnaio1, tnaio0 and tnbio1, tnbio0 bits can select the active trigger edge on the tpna and tpnb_0, tpnb_1, tpnb_2 pins to be a rising edge, falling edge or both edge types. if the tnaio1, tnaio0 and tnbio1, tnbio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpna and tpnb_0, tpnb_1, tpnb_2 pins, however it must be noted that the counter will continue to run. ccrp co?nter overflow ccrp int. fla? tnpf ccr? int. fla? tn?f tnon bit pa?se co?nter reset tnp?u bit res?me stop time yy xx ccr? val?e xx tm capt?re pin yy tn?io1? tn?io0 val?e 00 - risin? ed?e 01 - fallin? ed?e 11 - disable capt?re ?ctive ed?e ?ctive ed?e xx 10 - both ed?es ?ctive ed?es yy tn?m1? tn?m0 = 01 co?nter val?e etm ccra capture input mode note: 1. tnam [1:0] = 01 and active edge set by the tnaio [1:0] bits 2. the tm capture input pin active edge transfers he counter value to ccra 3. tncclr bit not used 4. no output function -- tnaoc and tnapol bits not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.20 114 ???? st 10 ? 2012 rev. 1.20 115 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver as the tpna and tpnb_0, tpnb_1, tpnb_2 pins are pin shared with other functions, care must be taken if the tm is in the capture input mode. this is because if the pin is setup as an output, then any transition s on this pin may cause an input capture operation to be executed. the tncclr, tnaoc, tnboc, tnapol and tnbpol bits are not used in this mode. ccrp co?nter overflow ccrp int. fla? tnpf ccrb int. fla? tnbf tnon bit pa?se co?nter reset tnp?u bit res?me stop yy xx ccrb val?e xx tm capt?re pin yy tnbio1? tnbio0 val?e 00 - risin? ed?e 01 - fallin? ed?e 11 - disable capt?re ?ctive ed?e ?ctive ed?e xx 10 - both ed?es ?ctive ed?es yy tnbm1? tnbm0 = 01 time co?nter val?e etm ccrb capture input mode note: 1. tnbm [1:0] = 01 and active edge set by the tnbio [1:0] bits 2. the tm capture input pin active edge transfers the counter value to ccrb 3. tncclr bit not used 4. no output function -- tnboc and tnbpol bits not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.20 114 ????st 10? 2012 rev. 1.20 115 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver touch key function each device provides multiple touch key functions. the touch key function is fully integrated and requires no external components, allowing touch key functions to be implemented by the simple manipulation of internal registers. touch key structure the touch keys are pin shared with the pc and pd logic i/o pins, as well as having dedicated pins. for the pin shared touch keys, the touch key function is chosen using register bits. keys are organised into groups of four , with each group known as a module and having a module number , m0 to m4. each module contains its own control logic circuits and register set. examination of the register names will reveal the module number it is referring to. device keys - n touch key module touch key shared i/o pin bs85b12-3 12 m0 k1~k4 pc0~pc3 m1 k5~k8 pc4~pc7 m2 k9~k12 dedicated pins bs85c20-3 /bs85c20-5 20 m0 k1~k4 pc0~pc3 m1 k5~k8 pc4~pc7 m2 k9~k12 dedicated pins m3 k13~k16 pd0~pd3 m4 k17~k20 pd4~pd7 touch key module/pin reference table touch key register defnition each touch key module, which contains four touch key functions, has its own suite of registers. the following table shows the register set for each touch key module. the mn within the register name refers to the t ouch key module number and has a range of m0 to m4. name usage tkmn16dh 16-bit c/f co ? nter hi ? h byte tkmn16dl 16-bit c/f co ? nter low byte tkmnc0 control re ? ister 0 key select tkmnc1 control re ? ister 1 internal reference. to ? ch pad reference. tkmnc2 control re ? ister 2 co ? nter on-off and clear control/reference clock control/tkst start bit tkmnc3 control re ? ister 3 counter overfow bits register listing
rev. 1.20 116 ???? st 10 ? 2012 rev. 1.20 117 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver register name bit 7 6 5 4 3 2 1 0 tkmn16dh d7 d6 d5 d4 d3 d2 d1 d0 tkmn16dl d7 d6 d5 d4 d3 d2 d1 d0 tkmnc0 mnmxs1 mnmxs0 d5 d4 d3 d2 d1 d0 tkmnc1 mnk4oen mnk3oen mnk2oen mnk1oen mnk4io mnk3io mnk2io mnk1io tkmnc2 mn16cton d6 mnst mnroen mnrcclr mn16ctclr d1 mnros tkmnc3 d9 d8 mnrcov mn16ctov d3 mnrovs2 mnrovs1 mnrovs0 register content summary tkmn16dh register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 module n 16-bit counter high byte contents tkmn16dl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 module n 16-bit counter low byte contents tkmnc0 register bit 7 6 5 4 3 2 1 0 name mnmxs1 mnmxs0 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bits 7~6 mnmxs1 , mnmxs0 : multiplexer key select bit module number mnmxs1 mnmxs0 m0 m1 m2 m3 m4 0 0 key 1 key 5 key 9 key 13 key 17 0 1 key 2 key 6 key 10 key 14 key 18 1 0 key 3 key 7 key 11 key 15 key 19 1 1 key 4 key 8 key 12 key 16 key 20 bit 5~0 d5~d0 : these bits m ? st be set to the binary val ? e " 011000 "
rev. 1.20 116 ????st 10? 2012 rev. 1.20 117 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver tkmnc1 register bit 7 6 5 4 3 2 1 0 name mnk4oen mnk3oen mnk2oen mnk1oen mnk4io mnk3io mnk2io mnk1io r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 for the bs85b12-3 n=0~2 while for the bs85c20-3 n=0~4. bits 7~4 mnk4oen~ mnk1oen : key selector control mnk4oen m0 m1 m2 m3 m4 key 4 key 8 key 12 key 16 key 20 0 disable 1 enable mnk3oen m0 m1 m2 m3 m4 key 3 key 7 key 11 key 15 key 19 0 disable 1 enable mnk2oen m0 m1 m2 m3 m4 key 2 key 6 key 10 key 14 key 18 0 disable 1 enable mnk1oen m0 m1 m2 m3 m4 key 1 key 5 key 9 key 13 key 17 0 disable 1 enable bits 3~0 i/o pin or t ouch key function select mnk4io m0 m1 m3 m4 pc3/key 4 pc7/key 8 pd3/key 16 pd7/key 20 0 i/o pin 1 to ? ch key mnk3io m0 m1 m3 m4 pc2/key 3 pc6/key 7 pd2/key 15 pd6/key 19 0 i/o pin 1 to ? ch key mnk2io m0 m1 m3 m4 pc1/key 2 pc5/key 6 pd1/key 14 pd5/key 18 0 i/o pin 1 to ? ch key mnk1io m0 m1 m3 m4 pc0/key 1 pc4/key 5 pd0/key 13 pd4/key 17 0 i/o pin 1 to ? ch key
rev. 1.20 118 ???? st 10 ? 2012 rev. 1.20 119 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver tkmnc2 register bit 7 6 5 4 3 2 1 0 name mn16cton d6 mnst mnroen mnrcclr mn16ctclr d1 mnros r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mn16cton : 16-bit c/f counter control 0: disable 1: enable bit 6 d6 : this bit must be cleared to zero. bit 5 mnst : t ime slot counter start control 0: time slot counter stopped 0 1: enable time slot counter. when this bit changes from low to high the time slot counter will be enabled and the touch sense procedure started. when the time slot counter has completed its counting an interrupt will be generated. bit 4 mnroen : reference clock control 0: disable 1: enable bit 3 mnrcclr : t ime slot counter clear control 0: no change 1: clear counter this bit must be frst set to 1 and then to 0. bit 2 mn16ctclr : 16-bit c/f counter clear control 0: no change 1: clear counter this bit must be frst set to 1 and then to 0. bit 1 d1 : this bit must be cleared to zero. bit 0 mnros : t ime slot counter clock source 0: reference clock 1: sense key oscillator m0:k4, m1:k8, m2:k12, m3:k16, m4:k20 tkmnc3 register bit 7 6 5 4 3 2 1 0 name d7 d6 mnrcov mn16ctov d3 mnrovs2 mnrovs1 mnrovs0 r/w r r r r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 d7, d6 : read only bits -- unknown values bit 5 mnrcov : t ime slot counter overfow fag 0: no overfow 1: overfow bit 4 mn16ctov : 16-bit c/f counter overfow fag 0: no overfow 1: overfow bit 3 d3 : this bit must be cleared to zero. bit 2~0 mnrovs2~mnrovs0 : t ime slot counter overfow time setup 000: 64 count 001: 128 count 010: 256 count 011: 512 count 100: 1024 count 101: 2048 count 110: 4096 count 111: 8192 count
rev. 1.20 118 ????st 10? 2012 rev. 1.20 119 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver touch key operation when a fnge r t ouches or i s i n proxi mity t o a t ouch pa d, t he c apacitance of t he pa d wi ll i ncrease. by using this capa citance variation to change slightly the frequency of the internal sense oscillator , touch act ions can be sensed by mea suring these frequency changes. using an internal programmable divider t he re ference c lock i s used t o ge nerated a fi xed t ime pe riod. by c ounting t he num ber of generated clock cycles from the sense oscillator during this fxed time period touch key actions can be determined. each touch key module contains four touch key inputs which are either dedicated touch key pins or are shared logical i/o pins. if shared, the desired function is selected using register bits. each touch key has its own independent sense oscillator . there are therefore four sense oscillators within each touch k ey m odule. e ach t ouch ke y m odule a lso h as i ts o wn i nterrupt v ector a nd se t o f i nterrupts fags. during this reference clock fixed interval, the number of clock cycles generated by the s ense oscillator is measured, and it is this value that is used to determine if a touch action has been made or not. at the end of the fxed reference clock time interval, a t ouch key interrupt signal will be generated. c/f & mux . 16-bit c/f counter 16-bit c/f counter int flag 16-bit c/f counter overflo w flag key 0 time slot counter int flag time slot counter overflow flag enable m u x reference clock time slot counter clock select time slot counter key 1 key 2 key 3 touch key (1 set = touch key*5) touch switch module block diagram
touch key or i/o function select
rev. 1.20 120 ???? st 10 ? 2012 rev. 1.20 121 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver touch key interrupt each touch key module, which consists of four touch keys, has two independent interrupts, one for each of the, 16-bit c/f counter and time slot counter. the time slot counter interrupt has its own interrupt vector while the 16-bit c/f counter interrupts are contained within the multi-function interrupts and therefore do not have their own vector . care must be taken during programming as the 16-bit c/f counter interrupt fags contained within the multi-function interrupts will not be automatically reset upon entry into the interrupt service routine but rathe r must be reset manually by the application program. more details regarding the touch key interrupts are located in the interrupt section of the datasheet. programming considerations after t he rel evant regi sters are se tup, t he t ouch key det ection process i s i nitiated t he cha nging t he mnst bit from low to high. this will enable and synchronise all releva nt oscillators. the mnrcov fag, whi ch i s t he t ime sl ot c ounter fa g wi ll go hi gh a nd re main hi gh unt il t he c ounter ove rfows. when this happens an interrupt signal will be generated. when the external touch key size and layout are defined, their related capacitances will then determine the sensor oscillator frequency.
rev. 1.20 120 ????st 10? 2012 rev. 1.20 121 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver serial interface module C sim these devices contain a serial interface module, which includes both the four line spi interface or the two line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. ha ving re latively si mple c ommunication prot ocols, t hese se rial i nterface t ypes a llow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memor y, etc. the sim pins are pin shared with other i/o pins and must be selected using the simen bit in the simc0 register . as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 register. spi interface the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either mas ter or s lave. a lthough the s pi interface s pecifcation can control multiple s lave devices from a single master , but this device provided only one scs pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices. spi interface operation the spi i nterface i s a f ull d uplex sy nchronous se rial d ata l ink. i t i s a f our l ine i nterface wi th p in names sdi , sdo, sc k a nd sc s. pi ns sdi a nd sdo a re t he se rial da ta i nput a nd se rial da ta output l ines, sck i s t he se rial cl ock l ine a nd sc s i s t he sl ave se lect l ine. as t he spi i nterface pins are pin-shared with normal i/o pins and with the i 2 c function pins, the spi interface must frst be enabled by setting the correct bits in the simc0 and simc2 registers. communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations b eing i mplemented b y t he m aster. t he ma ster a lso c ontrols t he c lock si gnal. as t he d evice only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit to "1" to enable scs pin function, set csen bit to "0" the scs pin will be as i/o function. spi master/slave connection the spi function in this device offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge the status of the spi interface pins is determined by a number of facto rs such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen.
rev. 1.20 122 ???? st 10 ? 2012 rev. 1.20 123 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver

? ?
? ? ?? ? ? ?? ? ? ? spi block diagram spi registers there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim2 sim1 sim0 pcken pckp1 pckp0 simen simd d7 d6 d5 d4 d3 d2 d1 d0 simc2 d7 d6 ckpolb ckeg mls csen wcol trf spi register list the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i2c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the spi bus, the device can read it from the simd register . any transmission or reception of data from the spi bus must be made via the simd register. simd register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x ? nknown there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi functio n, only by the i 2 c function. register simc0 is used to control the enable/disable function a nd t o se t t he da ta t ransmission c lock fre quency. al though not c onnected wi th t he spi function, the simc0 register is also used to control the peripheral clock prescaler . register simc2 is used for other control functions such as lsb/msb selection, write collision fag etc.
rev. 1.20 122 ????st 10? 2012 rev. 1.20 123 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver simc0 register bit 7 6 5 4 3 2 1 0 name sim2 sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f lirc 100: unused 101: spi slave mode 110: i 2 c slave mode 111: unused these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slav e select ion and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen : sim control 0: disable 1: enable the bi t is the overall on/of f control for the sim interface. when the simen bi t is cleared, the sdi, sdo, sck and scs, or sda and scl lines will be as i/o function and the s im operating current w ill be reduced to a minimum value. when the bit is high the sim interface is enabled. if the sim is configured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at t he pre vious se ttings whe n t he sime n bi t c hanges from l ow t o hi gh a nd shoul d therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c fags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as "0"
rev. 1.20 124 ???? st 10 ? 2012 rev. 1.20 125 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver simc2 register bit 7 6 5 4 3 2 1 0 name d7 d6 ckpolb ckeg mls csen wcol trf r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 undefned bit this bit can be read or written by user software program. bit 5 ckpolb : determines the base condition of the clock line 0: the sck line will be high when the clock is inactive 1: the sck line will be low when the clock is inactive the ckpolb bi t det ermines the base condit ion of the clock line, if the bi t is hi gh, then t he sck l ine wi ll be l ow whe n t he c lock i s i nactive. w hen t he ckpol b bi t i s low, then the sck line will be high when the clock is inactive. bit 4 ckeg : determines spi sck active clock edge type ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before data transfer is e xecuted ot herwise a n e rroneous c lock e dge m ay be ge nerated. t he ckpol b bi t determines t he ba se c ondition of t he c lock l ine, i f t he bi t i s hi gh, t hen t he sck l ine will be low when the clock is inactive. when the ckpolb bit is low , then the sck line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. bit 3 mls : spi data shift order 0: lsb 1: msb this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 csen : spi scs pin control 0: disable 1: enable the csen bit is used as an enable/disable for the scs pin. if this bit is low , then the scs pin will be disabled and as i/o function. if the bit is high the scs pin will be enabled and used as a select pin. bit 1 wcol : spi w rite collision fag 0: no collision 1: collision the wcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simd register during a data transfer operation . this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. bit 0 trf : spi t ransmit/receive complete fag 0: data is being transferred 1: spi data transmission is completed the trf bit is the t ransmit/receive complete fag and is set "1" automatically when an spi data transmission is complet ed, but must set to "0" by the applic ation program. it can be used to generate an interrupt.
rev. 1.20 124 ????st 10? 2012 rev. 1.20 125 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver spi communication after t he spi i nterface i s e nabled by se tting t he sime n bi t hi gh, t hen i n t he ma ster mode , whe n data is written to the simd register, transmission/reception will begin simultaneously. when the data transfer is complete, the trf fag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the s imd regis ter w ill be trans mitted and any data on the s di pin w ill be s hifted into the s imd register. the master should output an scs signal to enable the slave device before a clock signal is provi ded. t he sl ave da ta t o be t ransferred should be we ll prepa red at t he a ppropriate m oment relative t o t he sc s si gnal d epending u pon t he c onfgurations o f t he c kpolb b it a nd c keg b it. the accompanyin g timing diagram shows the relationship between the slave data and scs signal for various confgurations of the ckpolb and ckeg bits. the spi will continue to function even in the idle mode.
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? ? spi master mode timing

? ? ? ? ??? ? - ? ? ?? spi slave mode timing ckeg=0
rev. 1.20 126 ???? st 10 ? 2012 rev. 1.20 127 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver

? ???? ? ? ?? ? ?? ?? ? - ? ?? ?? ? ? ?? ? ? ? ? ?? ? ?? ?? ?? ? ? ?? ?? ???? ?? ? ?? ? ? ? ?? spi slave mode timing ckeg=1

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rev. 1.20 126 ????st 10? 2012 rev. 1.20 127 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom m emory e tc. or iginally d eveloped b y ph ilips, i t i s a t wo l ine l ow sp eed se rial i nterface for synchronous serial data transfer . the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c master slave bus connection i 2 c interface operation the i 2 c serial interface is a two line interf ace, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two device s communicate with each other on the bidirectional i 2 c bus, one is known as the master de vice a nd one a s t he sl ave de vice. bot h m aster a nd sl ave c an t ransmit a nd re ceive da ta, however, it is the master device that has overall control of the bus. for these devices, which only operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode.

? ? ? ? ? ?-? ? ? ? ?? ? ?? ? ? ? ? ? ? ? ? ? ? i 2 c block diagram
rev. 1.20 128 ???? st 10 ? 2012 rev. 1.20 129 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver the debounce tim e of the i 2 c interf ace uses the system clock to in ef fect add a debounce time to the external c lock t o re duce t he possi bility of gl itches on t he c lock l ine c ausing e rroneous ope ration. the debounce tim e, is 2 system clocks. t o achieve the required i 2 c data transfer speed, there exists a relation ship between the system clock, f sys , and the i 2 c debounce tim e. for either the i 2 c standard or fast mode operation, users must take care of the selected system clock frequency and the confgured debounce time to match the criterion shown in the following table. i 2 c debounce time selection i 2 c standard mode (100khz) i 2 c fast mode (400khz) 2 system clock debo ? nce f sys > 4mhz f sys > 10mhz i 2 c minimum f sys frequency
i 2 c registers there are four control registers associated with the i 2 c bus, simc0, simc1, sima and i2ct oc and one data register , simd. the simd register , which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the i 2 c bus, the micro controller can read it from the simd register . any transmission or reception of data from the i 2 c bus must be made via the simd register . the sim pins are pin shared with other i/o pins and must be selected using the simen bit in the simc0 register. note that the sima register also has the name simc2 which is used by the spi function. bit simen and bits sim2~sim0 in register simc0 are used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim2 sim1 sim0 pcken pckp1 pckp0 simen simc1 hcf h ?? s hbb htx tx ? k srw i ? mwu rx ? k simd d7 d6 d5 d4 d3 d2 d1 d0 sim ? iic ? 6 iic ? 5 iic ? 4 iic ? 3 iic ? 2 iic ? 1 iic ? 0 d0 i2ctoc i2ctoen i2ctof i2ctos5 i2ctos4 i2ctos3 i2ctos2 i2ctos1 i2ctos0 i 2 c register list
rev. 1.20 128 ????st 10? 2012 rev. 1.20 129 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver simc0 register bit 7 6 5 4 3 2 1 0 name sim2 sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f lirc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slav e select ion and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control described elsewhere bit 3~2 pckp1, pckp0 : select pck output pin frequency described elsewhere bit 1 simen : sim control 0: disable 1: enable the bi t is the overall on/of f control for the sim interface. when the simen bi t is cleared, the sdi, sdo, sck and scs, or sda and scl lines will be as i/o function and the s im operating current w ill be reduced to a minimum value. when the bit is high the sim interface is enabled. if the sim is configured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at t he pre vious se ttings whe n t he sime n bi t c hanges from l ow t o hi gh a nd shoul d therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c fags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as "0"
rev. 1.20 130 ???? st 10 ? 2012 rev. 1.20 131 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver simc1 register bit 7 6 5 4 3 2 1 0 name hcf h ?? s hbb htx tx ? k srw i ? mwu rx ? k r/w r r r r/w r/w r r/w r por 1 0 0 0 0 0 0 1 bit 7 hcf : i 2 c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haas : i 2 c bus address match fag 0: not address match 1: address match the hass fag i s t he a ddress m atch fag. t his fag i s used t o de termine i f t he sla ve device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 hbb : i 2 c bus busy fag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb fag is the i 2 c busy fag. t his fag will be "1" when the i 2 c bus is busy which will occur when a st art signal is detected. the fag will be set to "0" when the bus is free which will occur when a stop signal is detected. bit 4 htx : select i 2 c slave device is transmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter bit 3 txak : i 2 c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave do not send acknowledge fag the txak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txak bit to "0" before further data is received. bit 2 srw : i 2 c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the sr w f lag i s t he i 2 c sl ave r ead/write f lag. t his f lag d etermines wh ether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas fag is set high, the slave device will check the sr w fag to determine whether it should be in transmit mode or receive mode. if the sr w fag is high, the master is requesti ng to read data from the bus, so the slave device should be in transmit mode. when the sr w flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 iamwu : i 2 c address match wake-up control 0: disable 1: enable this b it sh ould b e se t t o " 1" t o e nable i 2c a ddress m atch wa ke-up f rom sl eep o r idle mode. if the iamwu bit has been set before entering either the sleep or idle mode to enable the i 2 c baddress match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation. bit 0 rxak : i 2 c bus receive acknowledge fag 0: slave receive acknowledge fag 1: slave do not receive acknowledge fag
rev. 1.20 130 ????st 10? 2012 rev. 1.20 131 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver the rx ak flag is the receiver acknow ledge flag. when the rx ak flag is " 0", i t means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks t he r xak fa g t o d etermine i f t he m aster r eceiver wi shes t o r eceive t he n ext b yte. the slave transmitter will therefore continue sending out data until the rxak fag is "1". when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. i2ctoc register bit 7 6 5 4 3 2 1 0 name i2ctoen i2ctof i2ctos5 i2ctos4 i2ctos3 i2ctos2 i2ctos1 i2ctos0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 i2ctoen : i 2 c t ime-out control 0: disable 1: enable bit 6 i2ctof : t ime-out fag 0: no time-out 1: time-out occurred bit 5~0 i2ctos5 ~ i2ctos0 : t ime-out t ime defnition i 2 c time-out clock source is f lirc /32. i 2 c t ime-out time is given by: [i2ctos5 : i2ctos0]+1) x (32/f lirc ) the simd registe r is used to store the data being transmitted and rece ived. the same register is used by both the spi and i 2 c functions. before the device writes data to the i 2 c bus, the act ual data to be transm itted must be placed in the simd regi ster. aft er the data is received from the i 2 c bus, the device can read it from the simd register . any transmission or reception of data from the i 2 c bus must be made via the simd register. simd register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x ? nknown sima register bit 7 6 5 4 3 2 1 0 name iic ? 6 iic ? 5 iic ? 4 iic ? 3 iic ? 2 iic ? 1 iic ? 0 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x ? nknown bit 7~1 iica6~ iica0 : i 2 c slave address iica6~ iica0 is the i 2 c slave address bit 6~bit 0. the sima register is also used by the spi interface but has the name simc2. the sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~1 of the sima register defne the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register , the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. bit 0 undefned bit this bit can be read or written by user software program.
rev. 1.20 132 ???? st 10 ? 2012 rev. 1.20 133 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver i 2 c bus communication communication on the i 2 c bus requires four separate steps, a st art signal, a slave device address transmission, a data transmission and finally a st op signal. when a st art signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the haas bit to determine whether the interrupt source originates from an address match or from the comple tion of an 8-bit data transfer . during a data transfer , note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/writ e bit whose value will be placed in the sr w bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must init ialise the bus, the following are steps to achieve this: step 1 set the sim2~sim0 and simen bits in the simc0 register to "1" to enable the i 2 c bus. step 2 write the slave address of the device to the i 2 c bus address register sima. step 3 set the sime and sim muti-function interrupt enable bit of the interrupt control register to enable the sim interrupt and multi-function interrupt.

? ? ? ? ? ? ? - ? ?? ? ? ? ? ? ? i 2 c bus initialisation flow chart i 2 c bus start signal the st art signal can only be generated by the master device connected to the i 2 c bus and not by the slave device. this st art signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a st art condition occurs when a high to low transition on the sda line takes place when the scl line remains high.
rev. 1.20 132 ????st 10? 2012 rev. 1.20 133 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver
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- ? ? note: * when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c communication timing diagram slave address the t ransmission o f a st art si gnal b y t he m aster wi ll b e d etected b y a ll d evices o n t he i 2 c b us. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the st art signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the maste r matche s the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal wil l be generat ed. the next bit fol lowing the address, which is the 8th bit, defnes the read/write status and will be saved to the sr w bit of the simc1 register . the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, t he haas bi t shoul d be e xamined t o se e whe ther t he i nterrupt sourc e ha s c ome from a matching slave address or from the completion of a data byte transfer . when a slave address is matched, the device must be placed in either the transmit mode and then w rite data to the s imd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c bus read/write signal the sr w bit in the simc1 registe r defnes whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver . if the sr w fag is "1" then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter . if the sr w fag is "0" then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver.
rev. 1.20 134 ???? st 10 ? 2012 rev. 1.20 135 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver i 2 c bus slave address acknowledge signal after the mas ter has trans mitted a calling addres s, any s lave device on the i 2 c bus , w hose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a st op signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the sr w fag to determine if it is to be a transmitter or a receiver . if the sr w fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to "1". if the sr w fag is low , then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to "0". i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb first and the lsb last. after receipt of 8-bi ts of da ta, t he re ceiver m ust t ransmit a n a cknowledge si gnal, l evel "0", be fore i t c an receive the next data byte. if the slave transmitter does not receive an acknowledge bit signal from the master receiver , then the slave transmitter will release the sda line to allow the master to send a st op signal to release the i 2 c bus. the corresponding data will be stored in the simd register . if setup as a transmitter , the slave device must frst write the data to be transmitted into the simd register. if setup as a receiver, the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a transmi tter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master.
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i 2 c bus isr flow chart
rev. 1.20 134 ????st 10? 2012 rev. 1.20 135 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver i 2 c time-out control in order to reduce the problem of i 2 c lockup due to reception of erroneous clock sources, clock, a time-out function is provided. if the clock source to the i 2 c is not received then after a fxed time period, the i 2 c circuitry and registers will be reset. the time-out counter starts counting on an i 2 c bus "st art" & "address match" condition, and is c leared b y a n sc l f alling e dge. b efore t he n ext sc l f alling e dge a rrives, i f t he t ime e lapsed i s greater than the time-out s etup by the i2ct oc regis ter, then a time-out condition w ill occur . the time-out function will stop when an i 2 c "stop" condition occurs.

i 2 c time-out when an i 2 c time -out counte r overfow occurs, the counter will stop and the i2ct oen bit will be cleared to zero and the i2ctf bit will be set high to indicate that a time-out condition as occurred. the t ime-out c ondition wi ll a lso ge nerate a n i nterrupt whi ch use s t he i 2 c i nterrrupt ve ctor. w hen an i 2 c tim e-out occurs the i 2 c inter nal circuitry will be reset and the registers will be reset into the following condition: register after i 2 c time-out simdr ? sim ? r ? simc0 no chan ? e simc1 reset to por condition i 2 c registers after time-out the i2ct of f ag can be cleared by the application program. there are 64 time-out periods w hich can be selected using bits in the i2ctoc register. the time-out time is given by the formula: ((1~64) 32)/f lirc . this gives a range of about 1ms to 64ms. note also that the lirc oscillator is continuously enabled.
rev. 1.20 136 ???? st 10 ? 2012 rev. 1.20 137 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver peripheral clock output the peripheral clock output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. peripheral clock operation as the peripheral clock output pin, pck, is shared with i/o line, the required pin function is chosen via pcken in the simc0 register . the peripheral clock function is controlled using the simc0 register. the clock source for the peripheral clock output can originat e from either the tm0 ccrp match frequency/2 or a divided ratio of the internal f sys clock. the pcken bit in the simc0 register is the overall on/of f control, setting pcken bit to "1" enables the peripheral clock, setting pcken bit t o "0" di sables i t. t he re quired di vision ra tio of t he syst em c lock i s se lected usi ng t he pc kp1 and pckp0 bits in the same register . if the devic e enters the sleep mode this will disable the peripheral clock output. simc0 register bit 7 6 5 4 3 2 1 0 name sim2 sim1 sim0 pcken pckpsc1 pckpsc0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2~sim0 : sim operating mode control described elsewhere bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckpsc1 , pckpsc0 : select pck output pin frequency 0: f sys 1: f sys /4 2: f sys /8 3: tm0 ccrp match frequency/2 bit 1 simen : sim control described elsewhere bit 0 unimplemented, read as "0"
rev. 1.20 136 ????st 10? 2012 rev. 1.20 137 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t ouch action or t imer module requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the devices contains several external interrupt and internal interrupts functions. the external interrupt is generated by the action of the external int pin, while the internal interrupts are generated by various internal functions such as the touch keys, t imer module, t ime base, sim etc. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the special purpose data memory , as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. the first is the intc0~intc3 registers which setup the primary interrupts, the second i s t he mfi 0~mfi5 r egisters wh ich se tup t he mu lti-function i nterrupts. fi nally t here i s a n integ register to setup the external interrupt trigger edge type. each regist er contai ns a number of enable bit s to enable or disa ble indivi dual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes global emi int pin intne intnf n=0 or 1 to ? ch key mod ? le tkmne tkmnf n=0~4 sim sim sif eeprom dee def m ? lti-f ? nction mfne mfnf n=0~5 time base tbne tbnf n=0 or 1 lvd lvf lve external peripheral xpe xpf tm tnpe tnpf n=0~2 tn ? e tn ? f n=0~2 tnbe tnbf n=1 interrupt register bit naming conventions
rev. 1.20 138 ???? st 10 ? 2012 rev. 1.20 139 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver interrupt register contents bs85b12-3 name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 simf int1f int0f sime int1e int0e emi intc1 tb0f tkm2f tkm1f tkm0f tb0e tkm2e tkm1e tkm0e intc2 mf3f mf2f mf1f mf0f mf3e mf2e mf1e mf0e mfi0 m116ctf d6 m016ctf d4 m116cte d2 m016cte d0 mfi1 t0 ? f t0pf m216ctf d4 t0 ? e t0pe m216cte d0 mfi2 t1bf t1 ? f t1pf t1be t1 ? e t1pe mfi3 def lvf xpf tb1f dee lve xpe tb1e bs85c20-3/bs85c20-5 name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 simf int1f int0f sime int1e int0e emi intc1 tb0f tkm2f tkm1f tkm0f tb0e tkm2e tkm1e tkm0e intc2 mf3f mf2f mf1f mf0f mf3e mf2e mf1e mf0e intc3 mf5f mf4f tkm4f tkm3f mf5e mf4e tkm4e tkm3e mfi0 m116ctf d6 m016ctf d4 m116cte d2 m016cte d0 mfi1 t0 ? f t0pf m216ctf d4 t0 ? e t0pe m216cte d0 mfi2 t1bf t1 ? f t1pf t1be t1 ? e t1pe mfi3 def lvf xpf tb1f dee lve xpe tb1e mfi4 m416ctf d6 m316ctf d4 m416cte d2 m316cte d0 mfi5 t2 ? f t2pf t2 ? e t2pe integ register C all devices bit 7 6 5 4 3 2 1 0 name int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 int1s1, int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1, int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges
rev. 1.20 138 ????st 10? 2012 rev. 1.20 139 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver intc0 register C all devices bit 7 6 5 4 3 2 1 0 name simf int1f int0f sime int1e int0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 simf : sim interrupt request fag 0: no request 1: interrupt request bit 5 int1f : int1 pin interrupt request fag 0: no request 1: interrupt request bit 4 int0f : int0 pin interrupt request fag 0: no request 1: interrupt request bit 3 sime : sim interrupt control 0: disable 1: enable bit 2 int1e : int1 pin interrupt control 0: disable 1: enable bit 1 int0e : int0 pin interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable intc1 register C all devices bit 7 6 5 4 3 2 1 0 name tb0f tkm2f tkm1f tkm0f tb0e tkm2e tkm1e tkm0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tb0f : t ime base 0 interrupt request fag 0: no request 1: interrupt request bit 6 tkm2f : t ouch key module 2 interrupt request fag 0: no request 1: interrupt request bit 5 tkm1f : t ouch key module 1 interrupt request fag 0: no request 1: interrupt request bit 4 tkm0f : t ouch key module 0 interrupt request fag 0: no request 1: interrupt request bit 3 tb0e : t ime base 0 interrupt control 0: disable 1: enable bit 2 tkm2e : t ouch key module 2 interrupt control 0: disable 1: enable bit 1 tkm1e : t ouch key module 1 interrupt control 0: disable 1: enable bit 0 tkm0e : t ouch key module 0 interrupt control 0: disable 1: enable
rev. 1.20 140 ???? st 10 ? 2012 rev. 1.20 141 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver intc2 register C all devices bit 7 6 5 4 3 2 1 0 name mf3f mf2f mf1f mf0f mf3e mf2e mf1e mf0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf3f : multi-function interrupt 3 request fag 0: no request 1: interrupt request bit 6 mf2f : multi-function interrupt 2 request fag 0: no request 1: interrupt request bit 5 mf1f : multi-function interrupt 1 request fag 0: no request 1: interrupt request bit 4 mf0f : multi-function interrupt 0 request fag 0: no request 1: interrupt request bit 3 mf3e : multi-function interrupt 3 control 0: disable 1: enable bit 2 mf2e : multi-function interrupt 2 control 0: disable 1: enable bit 1 mf1e : multi-function interrupt 1 control 0: disable 1: enable bit 0 mf0e : multi-function interrupt 0 control 0: disable 1: enable intc3 register C bs85c20-3/bs85c20-5 only bit 7 6 5 4 3 2 1 0 name mf5f mf4f tkm4f tkm3f mf5e mf4e tkm4e tkm3e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf5f : multi-function interrupt 5 request fag 0: no request 1: interrupt request bit 6 mf4f : multi-function interrupt 4 request fag 0: no request 1: interrupt request bit 5 tkm4f : t ouch key module 4 interrupt request fag 0: no request 1: interrupt request bit 4 tkm3f : t ouch key module 3 interrupt request fag 0: no request 1: interrupt request bit 3 mf5e : multi-function interrupt 5 control 0: disable 1: enable bit 2 mf4e : multi-function interrupt 4 control 0: disable 1: enable bit 1 tkm4e : t ouch key module 4 interrupt control 0: disable 1: enable bit 0 tkm3e : t ouch key module 3 interrupt control 0: disable 1: enable
rev. 1.20 140 ????st 10? 2012 rev. 1.20 141 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver mfi0 register C all devices bit 7 6 5 4 3 2 1 0 name m116ctf d6 m016ctf d4 m116cte d2 m016cte d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 m116ctf : t ouch key module 1 16-bit counter interrupt request fag 0: no request 1: interrupt request bit 6 d6 : this bit must be cleared to zero bit 5 m016ctf : t ouch key module 0 16-bit counter interrupt request fag 0: no request 1: interrupt request bit 4 d4 : this bit must be cleared to zero bit 3 m116cte : t ouch key module 1 16-bit timer interrupt control 0: disable 1: enable bit 2 d2 : this bit must be cleared to zero bit 1 m016cte : t ouch key module 0 16-bit timer interrupt control 0: disable 1: enable bit 0 d0 : this bit must be cleared to zero mfi1 register C all devices bit 7 6 5 4 3 2 1 0 name t0 ? f t0pf m216ctf d4 t0 ? e t0pe m216cte d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t0af : tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 t0pf : tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 m216ctf : t ouch key module 2 16-bit counter interrupt request fag 0: no request 1: interrupt request bit 4 d4 : this bit must be cleared to zero bit 3 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 2 t0pe : tm0 comparator p match interrupt control 0: disable 1: enable bit 1 m216cte : t ouch key module 2 16-bit counter interrupt control 0: disable 1: enable bit 0 d0 : this bit must be cleared to zero
rev. 1.20 142 ???? st 10 ? 2012 rev. 1.20 143 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver mfi2 register C all devices bit 7 6 5 4 3 2 1 0 name t1bf t1 ? f t1pf t1be t1 ? e t1pe r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 t1bf : tm1 comparator b match interrupt request fag 0: no request 1: interrupt request bit 5 t1af : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf : tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as "0" bit 2 t1be : tm1 comparator b match interrupt control 0: disable 1: enable bit 1 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable mfi3 register C all devices bit 7 6 5 4 3 2 1 0 name def lvf xpf tb1f dee lve xpe tb1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 def : data eeprom interrupt request fag 0: no request 1: interrupt request bit 6 lvf : lvd interrupt request fag 0: no request 1: interrupt request bit 5 xpf : external peripheral interrupt request fag 0: no request 1: interrupt request bit 4 tb1f : t ime base 1 interrupt request fag 0: no request 1: interrupt request bit 3 dee : data eeprom interrupt control 0: disable 1: enable bit 2 lve : lvd interrupt control 0: disable 1: enable bit 1 xpe : external peripheral interrupt control 0: disable 1: enable bit 0 tb1e : t ime base 1 interrupt control 0: disable 1: enable
rev. 1.20 142 ????st 10? 2012 rev. 1.20 143 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver mfi4 register C bs85c20-3/bs85c20-5 only bit 7 6 5 4 3 2 1 0 name m416ctf d6 m316ctf d4 m416cte d2 m316cte d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 m416ctf : t ouch key module 4 16-bit counter interrupt request fag 0: no request 1: interrupt request bit 6 d6 : this bit must be cleared to zero bit 5 m316ctf : t ouch key module 3 16-bit counter interrupt request fag 0: no request 1: interrupt request bit 4 d4 : this bit must be cleared to zero bit 3 m416cte : t ouch key module 4 16-bit counter interrupt control 0: disable 1: enable bit 2 d2 : this bit must be cleared to zero bit 1 m316cte : t ouch key module 3 16-bit counter interrupt control 0: disable 1: enable bit 0 d0 : this bit must be cleared to zero mfi5 register C bs85c20-3/bs85c20-5 only bit 7 6 5 4 3 2 1 0 name t2 ? f t2pf t2 ? e t2pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 t2af : tm2 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t2pf : tm2 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 t2ae : tm2 comparator a match interrupt control 0: disable 1: enable bit 0 t2pe : tm2 comparator p match interrupt control 0: disable 1: enable
rev. 1.20 144 ???? st 10 ? 2012 rev. 1.20 145 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver interrupt operation when t he c onditions f or a n i nterrupt e vent o ccur, su ch a s a t ouch ke y c ounter o verfow, t imer module overfow, etc. the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt e nable bi t. if t he e nable bi t i s set hi gh t hen t he program wi ll j ump t o i ts re levant ve ctor; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a jmp instruction which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti instruction, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . o nce an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decrement ed. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is applied. all of the interrupt request fags when set will wake-up the device if it is in sleep or idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device enters the sleep or idle mode.
rev. 1.20 144 ????st 10? 2012 rev. 1.20 145 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver

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rev. 1.20 146 ???? st 10 ? 2012 rev. 1.20 147 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver external interrupt the external interrupt is controlled by signal transitions on the int0 and int1 pins. an external interrupt request will take place when the external interrupt request fag, int0f or int1f , is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e or int1e, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the externa l interrupt functio n and to choose the trigger edge type. as the external interrupt pin is pin-shared with i/o pin, it can only be configured as external interrupt pin if the external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interrupt is enabled, the stack is not full and the correct transition type appears on the extern al interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the external interrupt r equest fa g, i ntf, wi ll b e a utomatically r eset a nd t he e mi b it wi ll b e a utomatically c leared to disable other inte rrupts. note that any pul l-high resistor sel ections on the externa l interrupt pin will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. multi-function interrupt within these devices there are four or six multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from the t ouch key module, timer module, low v oltage detector, eeprom, external peripheral and t ime base interrupt sources. a multi-function interrupt request will take place when any of the multi-function interrupt request flags, mfnf are set. the multi-function interrupt flags will be set when any of their included functions generate an interrupt request fag. t o allow the program to branch to its respective interrupt vector address, when the multi-func tion interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi-function re quest fl ag, wi ll be a utomatically re set a nd t he e mi bi t wi ll be a utomatically cleared to disable other interrupts. however, i t m ust be not ed t hat, a lthough t he mul ti-function int errupt fa gs wi ll be a utomatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the t ouch key module timer interrupts, will not be automatically reset and must be manually reset by the application program. time base interrupts the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the t ime base overfows, a subroutine call to their respective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts.
rev. 1.20 146 ????st 10? 2012 rev. 1.20 147 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the t ime base interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section.

time base structure C bs85b12-3/bs85c20-3

time base structure C bs85c20-5 tbc register C bs85c12-3/bs85c20-3 bit 7 6 5 4 3 2 1 0 name tbon tbck tb11 tb10 d3 tb02 tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 0 1 1 1 bit 7 tbon : tb0 and tb1 control 0: disable 1: enable bit 6 tbck : select f tb clock 0: f tbc 1: f sys /4 bit 5~4 tb11 ~tb10 : select t ime base 1 t ime-out period 0: 4096/f tb 1: 8192/f tb 2: 16384/f tb 3: 32768/f tb bit 3 undefned bit this bit can be read or written by user software program. bit 2~0 tb02~tb00 : select t ime base 0 t ime-out period 0: 256/f tb 1: 512/f tb 2: 1024/f tb 3: 2048/f tb 4: 4096/f tb 5: 8192/f tb 6: 16384/f tb 7: 32768/f tb
rev. 1.20 148 ???? st 10 ? 2012 rev. 1.20 149 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver tbc register C bs85c20-5 bit 7 6 5 4 3 2 1 0 name tbon tbck tb11 tb10 lxtlp tb02 tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 0 1 1 1 bit 7 tbon : tb0 and tb1 control 0: disable 1: enable bit 6 tbck : select f tb clock 0: f tbc 1: f sys /4 bit 5~4 tb11 ~tb10 : select t ime base 1 t ime-out period 0: 4096/f tb 1: 8192/f tb 2: 16384/f tb 3: 32768/f tb bit 3 lxtlp : lxt low power control 0: disable 1: enable bit 2~0 tb02~tb00 : select t ime base 0 t ime-out period 0: 256/f tb 1: 512/f tb 2: 1024/f tb 3: 2048/f tb 4: 4096/f tb 5: 8192/f tb 6: 16384/f tb 7: 32768/f tb external peripheral interrupt the exte rnal peripheral interrupt operates in a similar way to the exter nal interrupt and is contained within the multi-function interrupt. a peripheral interrupt request will take place when the external peripheral interrupt request fag, xpf , is set, which occurs when a negative edge transition appears on t he pint pi n. t o a llow t he progra m t o bra nch t o i ts re spective i nterrupt ve ctor a ddress, t he global i nterrupt e nable bi t, e mi, e xternal pe ripheral i nterrupt e nable bi t, xpe , a nd a ssociated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full a nd a ne gative t ransition a ppears on t he e xternal peri pheral int errupt pi n, a subrout ine c all t o the re spective mu lti-function int errupt, wi ll t ake pl ace. w hen t he e xternal pe ripheral int errupt i s serviced, t he e mi bi t wi ll be a utomatically c leared t o di sable ot her i nterrupts, ho wever on ly t he multi-function interrupt request fag will be also automatically cleared. as the xpf fag will not be automa tically cleared, it has to be cleared by the application program. the external peripheral interrupt pin is pin-shared with several other pins with dif ferent functions. it must therefore be properly confgured to enable it to operate as an external peripheral interrupt pin.
rev. 1.20 148 ????st 10? 2012 rev. 1.20 149 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver lvd interrupt the l ow v oltage de tector i nterrupt i s c ontained wi thin t he mu lti-function i nterrupt. an l vd interrupt reques t w ill take place w hen the l vd interrupt request flag, l vf, is s et, w hich occurs when the low v oltage detector function detects a low power supply voltage. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low v oltage interrupt enable bit, l ve, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage conditio n occurs, a subroutine call to the multi-function interrupt vector , will take place. when the low v oltage interrupt is serviced, the emi bit wi ll be aut omatically cl eared t o disable othe r i nterrupts, however only t he mul ti-function interrupt request fag will be also automatically cleared. as the l vf fag will not be automatically cleared, it has to be cleared by the application program. tm interrupts the compact and standard t ype tms have two interrupts each, while the enhanced t ype tm has three interrupts. all of the tm interrupts are contained within the multi-function interrupts. for each of t he com pact a nd st andard t ype t ms t here a re t wo i nterrupt re quest fa gs t npf a nd t naf a nd two enable bits tnpe and tnae. for the enhanced t ype tm there are three interrupt request fags tnpf, tnaf and tnbf and three enable bits tnpe, tnae and tnbe. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p, a or b match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. eeprom interrupt the eep rom interrupt, is contained w ithin the m ulti-function interrupt. a n eep rom interrupt request will take place when the eeprom interrupt request fag, def , is set, which occurs when an eeprom w rite cycle ends. t o allow the program to branch to its respective interrupt vector address, t he g lobal i nterrupt e nable b it, e mi, e eprom i nterrupt e nable b it, de e, a nd a ssociated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom w rite cycle ends, a subroutine call to the respective multi-function interrupt vector, will take place. when the eeprom interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the def fag will not be automatically cleared, it has to be cleared by the application program. touch key interrupts for a t ouch key interrupt to occur , the global interrupt enable bit, emi, and the corresponding t ouch key interrupt enable tkmne must be frst set. an actual t ouch key interrupt will take place when the touch key request fag. tkmnf , is set, a situation that will occur when the 13-bit time slot counter in the relevant t ouch key module overfows. when the interrupt is enabled, the stack is not full and the touch ke y t ime sl ot c ounter o verflow oc curs, a sub routine c all t o t he re levant t ouch ke y i nterrupt vector, wi ll t ake pl ace. w hen t he i nterrupt i s se rviced, t he t ouch ke y i nterrupt re quest fa g, t kmnf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts.
rev. 1.20 150 ???? st 10 ? 2012 rev. 1.20 151 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver sim interrupt a sim in terrupt re quest wi ll t ake pl ace whe n t he sim in terrupt re quest fa g, simf , i s se t, whi ch occurs when a byte of data has been received or transmitted by the sim interface. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, sime, must frst be set. when the interrupt is enabled, the st ack i s not ful l a nd a byt e of da ta ha s be en t ransmitted or re ceived by t he sim i nterface, a subroutine call to the respective interrupt vector , will take place. when the serial interface interrupt is serviced, the sim interrupt request fag, sif , will be automatically cleared and the emi bit will be automatically cleared to disable other interrupts. interrupt wake-up function each of the int errupt funct ions has the ca pability of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions o n t he e xternal i nterrupt p ins, a l ow p ower su pply v oltage o r c omparator i nput c hange may cause their respective interrupt fag to be set high and consequent ly generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no ef fect on the interrupt wake-up function. programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the multi-function interrupt request flags, mfnf , will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the "call" instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n sl eep o r i dle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as onl y t he progr am co unter i s pu shed ont o t he st ack, t hen whe n t he i nterrupt i s se rviced, i f t he contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.20 150 ????st 10? 2012 rev. 1.20 151 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver low voltage detector C lvd each device has a low v oltage detector function, also known as l vd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low v oltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name l vdc. three bits in this register , vl vd2~vlvd0, are used to select one of eight fxed voltages below which a low volta ge condition will be detemined. a low voltage condition is indicated when the l vdo bit is set. if the l vdo bit is low , this indicates that the v dd voltage is above the preset low voltage value. the l vden bit is used to control the overall on/of f function of the low voltage detector . setting the bit high will enabl e the low voltage detector . clearing the bit to zero will switch of f the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 name lvdo lvden vlvd2 vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 lvdo : lvd output flag 0: no low v oltage detect 1: low v oltage detect bit 4 lvden : low v oltage detector control 0: disable 1: enable bit 3 unimplemented, read as "0" bit 2~0 vlvd2 ~ vlvd0 : select lvd v oltage 000: undefned 001: undefned 010: undefned 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.2v
rev. 1.20 152 ???? st 10 ? 2012 rev. 1.20 153 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver lvd operation the low v oltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed volta ge level stored in the l vdc register . this has a range of between 2.0v and 4.2v . when the power supply voltage, v dd , falls below this pre-determined value, the l vdo bit will be set high indicating a low power supply voltage condition. the low v oltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the l vden bit is high. after enabling the low voltage detector , a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly , at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. lvd operation the low v oltage detector also has its own interrupt which is contained within one of the multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the l vdo bit. the interrupt will only be generated after a delay of t lvd after the l vdo bit has been set high by a low voltage condition. when the device is powered down the low v oltage detector will rema in active if the l vden bit is high. in this case, the l vf interrupt request fag will be set, causing an interru pt to be generated if v dd falls below the preset l vd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low v oltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode. lcd driver C scom and sseg function the devic es can drive lcd panels by simulating lcd signals on their i/o pins using the application program. both command and segment signals can be emulated in this way. lcd operation the lcd driving common pins, scom0~scom3, and segment pins, sseg0~ssegn, are pin shared with other i/o pins. these lcd driving pins are confgured using a series of lcd control registers which in addition to controlling the overall on/of f function also controls the bias voltage setup function. this enables the lcd com and seg driver to generate the necessary v ss , (1/3)v dd , (2/3)v dd voltage and v dd levels for full lcd 1/3 bias operation. the slcden bit in the lcd control register is the overall master control for the lcd driver , and this bi t i s use d i n c onjunction wi th t he comne n a nd se gnen bi ts t o se lect whi ch i/ o port pi ns are used for lcd driving. note that the port control register does not need to frst setup the pins as outputs to enable the lcd driver operation.
rev. 1.20 152 ????st 10? 2012 rev. 1.20 153 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver
lcd driver structure the acco mpanying waveform diagram shows a typical 1/3 bias lcd waveform generated using the application program. note that the depiction of a "1" in the diagram illustrates an illuminated lcd pixel. the com signal polarity generated on pins scom0~scom3, whether 0 or 1, are generated using the corresponding i/o data registers, which are bits pb0~pb3 in the pb register. note: the logical values shown in the diagram are the pb i/o register values, pb0~pb3. 1/3 bias lcd waveform
rev. 1.20 154 ???? st 10 ? 2012 rev. 1.20 155 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver a cyclic lcd waveform includes two frames, known as frame 0 and frame 1 for which the following offers a functional explanation. in frame 0 to select frame 0 clear the frame bit to 0. in frame 0, the com signal output can have a value of v dd , or have a vbias value of 1/3v dd . the seg signal can have a value of v ss , or have a vbias value of 2/3v dd . in frame 1 in f rame 1 , t he c om si gnal o utput c an h ave a v alue o f vss, h ave a vb ias v alue o f 2 /3v dd . t he se g signal can have a value of v dd have a vbias value of 1/3v dd . the com0~comn waveform is controlled by the application program using the frame bit, and the corresponding i/o data register for the respective com pin to determine whether the com0~comn output has a value of either v dd , v ss or vbias. the seg0~segm waveform is controlled in a similar way using the frame bit and the corres ponding i/o data regis ter for the respective seg pin to determine whether the seg0~segn output has a value of either v dd , v ss or vbias. lcd bias control the lcd com and seg driver enable a range of selections to be provided to suit the requirement of the lcd panel which are being used. the bias resistor choice is implemented using the isel1 and isel0 bits in the lcd control register. lcd driver registers slcdc0 register bit 7 6 5 4 3 2 1 0 name fr ? me isel1 isel0 slcden com3en com2en com1en com0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 frame : present frame output select C frame 0 or frame 1 0: frame 0 1: frame 1 bit 6~5 isel1 , isel0 : scom and sseg operating current selection C v dd =5v 0: 25 a 1: 50 a 2: 100 a 3: 200 a bit 4 slcden : scom and sseg module on/off control 0: disable 1: enable the scomn and ssegm lines can be enabled using comnen and segmen if slcden=1. when slcden=0, then the scomn and ssegm outputs will be fxed at a vdd level. bit 3 com3en : scom3 or other function selection 0: other function 1: scom3 bit 2 com2en : scom2 or other function selection 0: other function 1: scom2 bit 1 com1en : scom1 or other function selection 0: other function 1: scom1 bit 0 com0en : scom0 or other function selection 0: other function 1: scom0
rev. 1.20 154 ????st 10? 2012 rev. 1.20 155 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver slcdc1 register bit 7 6 5 4 3 2 1 0 name seg7en seg6en seg5en seg4en seg3en seg2en seg1en seg0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 seg7en~seg0en : sseg7~sseg0 or other function selection 0: other function 1: sseg7~sseg0 slcdc2 register C bs85b12-3 bit 7 6 5 4 3 2 1 0 name seg13en seg12en seg11en seg10en seg9en seg8en r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5~0 seg13en~seg8en : sseg13~sseg8 or other function selection 0: other function 1: sseg13~sseg8 slcdc2 register C bs85c20-3/bs85c20-5 bit 7 6 5 4 3 2 1 0 name seg15en seg14en seg13en seg12en seg11en seg10en seg9en seg8en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5~0 seg15en~seg8en : sseg15~sseg8 or other function selection 0: other function 1: sseg15~sseg8 slcdc3 register C bs85c20-3/bs85c20-5 bit 7 6 5 4 3 2 1 0 name tck2ps seg21en seg20en seg19en seg18en seg17en seg16en r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 tck2ps : tck2 pin remapping control described elsewhere bit 6 unimplemented, read as "0" bit 5~0 seg21en~seg16en : sseg21~sseg16 or other function selection 0: other function 1: sseg21~sseg16
rev. 1.20 156 ???? st 10 ? 2012 rev. 1.20 157 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver led driver the devices contain an led driver function of fering high current output drive capability which can be used to drive external leds. led driver operation depending upon which device is chosen various i/o pins have a capability of providing led high current drive outputs. device led drive pins bs85b12-3 p ? 0~p ? 7 (hi ? h so ? rce c ? rrent) pb0~pb5 (hi ? h sink c ? rrent) bs85c20-3 /bs85c20-5 p ? 0~p ? 7 (hi ? h so ? rce c ? rrent) pb0~pb7 (hi ? h sink c ? rrent) pe0~pe5 (hi ? h so ? rce c ? rrent) whether a normal current sink capability or high current sink capability is used, the selection is made using the sledcn registers. led driver registers sledc0 register C bs85b12-3 bit 7 6 5 4 3 2 1 0 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5~0 d5~d0 : pb5~pb0 i/o output sink current select 0: normal output sink current 1: 2 output sink current sledc0 register C bs85c20-3/bs85c20-5 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : pb7~pb0 i/o output sink current select 0: normal output sink current 1: 2 output sink current sledc1 register C all devices bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : pa7~pa0 i/o output source current select 0: normal output source current 1: 2 output source current sledc2 register C bs85c20-3/bs85c20-5 bit 7 6 5 4 3 2 1 0 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5~0 d5~d0 : pe5~pe0 i/o output source current select 0: normal output source current 1: 2 output source current
rev. 1.20 156 ????st 10? 2012 rev. 1.20 157 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver application circuits
?? ? ? ? ? ?? ? ? ?- ? ?-? ? ?-? ? ? ? ? ? ? ?? ? ??
note: "#" may be resistor or capacitor. the resistance of "#" must be greater than 1 k or the capacitance of "#" must be less than 1nf.
rev. 1.20 158 ???? st 10 ? 2012 rev. 1.20 159 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.20 158 ????st 10? 2012 rev. 1.20 159 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been carried out. this is done by placing a return ins truction " ret" in the s ubroutine w hich w ill cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is take n care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "hal t" i nstruction f or po wer-down o perations a nd i nstructions t o c ontrol t he o peration o f the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.20 160 ???? st 10 ? 2012 rev. 1.20 161 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic ? dd ?? [m] ? dd data memory to ? cc 1 z ? c ? ? c ? ov ? ddm ?? [m] ? dd ? cc to data memory 1 note z ? c ? ? c ? ov ? dd ?? x ? dd immediate data to ? cc 1 z ? c ? ? c ? ov ? dc ?? [m] ? dd data memory to ? cc with carry 1 z ? c ? ? c ? ov ? dcm ?? [m] ? dd ? cc to data memory with carry 1 note z ? c ? ? c ? ov sub ?? x s ? btract immediate data from the ? cc 1 z ? c ? ? c ? ov sub ?? [m] s ? btract data memory from ? cc 1 z ? c ? ? c ? ov subm ?? [m] s ? btract data memory from ? cc with res ? lt in data memory 1 note z ? c ? ? c ? ov sbc ?? [m] s ? btract data memory from ? cc with carry 1 z ? c ? ? c ? ov sbcm ?? [m] s ? btract data memory from ? cc with carry ? res ? lt in data memory 1 note z ? c ? ? c ? ov d ?? [m] decimal adj ? st ? cc for ? ddition with res ? lt in data memory 1 note c logic operation ? nd ?? [m] lo ? ical ? nd data memory to ? cc 1 z or ?? [m] lo ? ical or data memory to ? cc 1 z xor ?? [m] lo ? ical xor data memory to ? cc 1 z ? ndm ?? [m] lo ? ical ? nd ? cc to data memory 1 note z orm ?? [m] lo ? ical or ? cc to data memory 1 note z xorm ?? [m] lo ? ical xor ? cc to data memory 1 note z ? nd ?? x lo ? ical ? nd immediate data to ? cc 1 z or ?? x lo ? ical or immediate data to ? cc 1 z xor ?? x lo ? ical xor immediate data to ? cc 1 z cpl [m] complement data memory 1 note z cpl ? [m] complement data memory with res ? lt in ? cc 1 z increment & decrement inc ? [m] increment data memory with res ? lt in ? cc 1 z inc [m] increment data memory 1 note z dec ? [m] decrement data memory with res ? lt in ? cc 1 z dec [m] decrement data memory 1 note z rotate rr ? [m] rotate data memory ri ? ht with res ? lt in ? cc 1 none rr [m] rotate data memory ri ? ht 1 note none rrc ? [m] rotate data memory ri ? ht thro ?? h carry with res ? lt in ? cc 1 c rrc [m] rotate data memory ri ? ht thro ?? h carry 1 note c rl ? [m] rotate data memory left with res ? lt in ? cc 1 none rl [m] rotate data memory left 1 note none rlc ? [m] rotate data memory left thro ?? h carry with res ? lt in ? cc 1 c rlc [m] rotate data memory left thro ?? h carry 1 note c
rev. 1.20 160 ????st 10? 2012 rev. 1.20 161 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver mnemonic description cycles flag affected data move mov ?? [m] move data memory to ? cc 1 none mov [m] ?? move ? cc to data memory 1 note none mov ?? x move immediate data to ? cc 1 none bit operation clr [m].i clear bit of data memory 1 note none set [m].i set bit of data memory 1 note none branch jmp addr j ? mp ? nconditionally 2 none sz [m] skip if data memory is zero 1 note none sz ? [m] skip if data memory is zero with data movement to ? cc 1 note none sz [m].i skip if bit i of data memory is zero 1 note none snz [m].i skip if bit i of data memory is not zero 1 note none siz [m] skip if increment data memory is zero 1 note none sdz [m] skip if decrement data memory is zero 1 note none siz ? [m] skip if increment data memory is zero with res ? lt in ? cc 1 note none sdz ? [m] skip if decrement data memory is zero with res ? lt in ? cc 1 note none c ? ll addr s ? bro ? tine call 2 none ret ret ? rn from s ? bro ? tine 2 none ret ?? x ret ? rn from s ? bro ? tine and load immediate data to ? cc 2 none reti ret ? rn from interr ? pt 2 none table read t ? brdc [m] read table to tblh and data memory 2 note none t ? brdl [m] read table (last pa ? e) to tblh and data memory 2 note none miscellaneous nop no operation 1 none clr [m] clear data memory 1 note none set [m] set data memory 1 note none clr wdt clear watchdo ? timer 1 to ? pdf clr wdt1 pre-clear watchdo ? timer 1 to ? pdf clr wdt2 pre-clear watchdo ? timer 1 to ? pdf sw ? p [m] swap nibbles of data memory 1 note none sw ? p ? [m] swap nibbles of data memory with res ? lt in ? cc 1 none h ? lt enter power down mode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. f or the " clr wd t1" and " clr wd t2" ins tructions the t o and p df flags may be af fected by the execution status. the t o and pdf flags are cleared after both "clr wdt1" and "clr wdt2" instructions are consecutively executed. otherwise the t o and pdf fags remain unchanged.
rev. 1.20 162 ???? st 10 ? 2012 rev. 1.20 163 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
rev. 1.20 162 ????st 10? 2012 rev. 1.20 163 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt1 pre-clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re a ll c leared. n ote t hat t his instruction w orks in conjunction w ith c lr w dt2 a nd m ust b e e xecuted al ternately w ith c lr w dt2 to h ave effect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt2 w ill have no e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt2 pre-clear w atchdog t imer description the t o, p df f ags and t he w dt are all cleared. n ote t hat t his i nstruction w orks i n conjunction with c lr w dt1 a nd m ust b e e xecuted al ternately w ith c lr w dt1 to h ave e ffect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt1 w ill h ave n o e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z
rev. 1.20 164 ???? st 10 ? 2012 rev. 1.20 165 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [ m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.20 164 ????st 10? 2012 rev. 1.20 165 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none
rev. 1.20 166 ???? st 10 ? 2012 rev. 1.20 167 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none
rev. 1.20 166 ????st 10? 2012 rev. 1.20 167 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none
rev. 1.20 168 ???? st 10 ? 2012 rev. 1.20 169 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c
rev. 1.20 168 ????st 10? 2012 rev. 1.20 169 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.20 170 ???? st 10 ? 2012 rev. 1.20 171 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver tabrdc [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.20 170 ????st 10? 2012 rev. 1.20 171 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for the latest version of the package information. 24-pin skdip (300mil) outline dimensions fig1. full lead packages fig2. 1/2 lead packages ms-001d (see fg1) symbol dimensions in inch min. nom. max. ? 1.230 D 1.280 b 0.240 D 0.280 c 0.115 D 0.195 d 0.115 D 0.150 e 0.014 D 0.022 f 0.045 D 0.070 g D 0.100 D h 0.300 D 0.325 i D 0.430 D symbol dimensions in mm min. nom. max. ? 31.24 D 32.51 b 6.10 D 7.11 c 2.92 D 4.95 d 2.92 D 3.81 e 0.36 D 0.56 f 1.14 D 1.78 g D 2.54 D h 7.62 D 8.26 i D 10.92 D
rev. 1.20 172 ???? st 10 ? 2012 rev. 1.20 173 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver ms-001d (see fg2) symbol dimensions in inch min. nom. max. ? 1.160 D 1.195 b 0.240 D 0.280 c 0.115 D 0.195 d 0.115 D 0.150 e 0.014 D 0.022 f 0.045 D 0.070 g D 0.100 D h 0.300 D 0.325 i D 0.430 D symbol dimensions in mm min. nom. max. ? 29.46 D 30.35 b 6.10 D 7.11 c 2.92 D 4.95 d 2.92 D 3.81 e 0.36 D 0.56 f 1.14 D 1.78 g D 2.54 D h 7.62 D 8.26 i D 10.92 D
rev. 1.20 172 ????st 10? 2012 rev. 1.20 173 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver ms-095a (see fg2) symbol dimensions in inch min. nom. max. ? 1.145 D 1.185 b 0.275 D 0.295 c 0.120 D 0.150 d 0.110 D 0.150 e 0.014 D 0.022 f 0.045 D 0.060 g D 0.100 D h 0.300 D 0.325 i D 0.430 D symbol dimensions in mm min. nom. max. ? 29.08 D 30.10 b 6.99 D 7.49 c 3.05 D 3.81 d 2.79 D 3.81 e 0.36 D 0.56 f 1.14 D 1.52 g D 2.54 D h 7.62 D 8.26 i D 10.92 D
rev. 1.20 174 ???? st 10 ? 2012 rev. 1.20 175 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver 24-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. ? 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c ? 0.598 0.613 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013 0 8 symbol dimensions in mm min. nom. max. ? 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c ? 15.19 15.57 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33 0 8
rev. 1.20 174 ????st 10? 2012 rev. 1.20 175 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver 24-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. ? 0.228 0.244 b 0.150 0.157 c 0.008 0.012 c ? 0.335 0.346 d 0.054 0.060 e 0.025 f 0.004 0.010 g 0.022 0.028 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. ? 5.79 6.20 b 3.81 3.99 c 0.20 0.30 c ? 8.51 8.79 d 1.37 1.52 e 0.64 f 0.10 0.25 g 0.56 0.71 h 0.18 0.25 0 8
rev. 1.20 176 ???? st 10 ? 2012 rev. 1.20 177 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver 28-pin skdip (300mil) outline dimensions symbol dimensions in inch min. nom. max. ? 1.375 D 1.395 b 0.278 D 0.298 c 0.125 D 0.135 d 0.125 D 0.145 e 0.016 D 0.020 f 0.050 D 0.070 g D 0.100 D h 0.295 D 0.315 i D 0.375 D symbol dimensions in mm min. nom. max. ? 34.93 D 35.43 b 7.06 D 7.57 c 3.18 D 3.43 d 3.18 D 3.68 e 0.41 D 0.51 f 1.27 D 1.78 g D 2.54 D h 7.49 D 8.00 i D 9.53 D
rev. 1.20 176 ????st 10? 2012 rev. 1.20 177 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver 28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. ? 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c ? 0.697 0.713 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013 0 8 symbol dimensions in mm min. nom. max. ? 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c ? 17.70 18.11 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33 0 8
rev. 1.20 178 ???? st 10 ? 2012 rev. 1.20 179 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver 28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. ? 0.228 0.244 b 0.150 0.157 c 0.008 0.012 c ? 0.386 0.394 d 0.054 0.060 e 0.025 f 0.004 0.010 g 0.022 0.028 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. ? 5.79 6.20 b 3.81 3.99 c 0.20 0.30 c ? 9.80 10.01 d 1.37 1.52 e 0.64 f 0.10 0.25 g 0.56 0.71 h 0.18 0.25 0 8
rev. 1.20 178 ????st 10? 2012 rev. 1.20 179 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver 44-pin qfp (10mm 10mm) outline dimensions symbol dimensions in inch min. nom. max. ? 0.512 0.528 b 0.390 0.398 c 0.512 0.528 d 0.390 0.398 e 0.031 f 0.012 g 0.075 0.087 h 0.106 i 0.010 0.020 j 0.029 0.037 k 0.004 0.008 l 0.004 0 7 symbol dimensions in mm min. nom. max. ? 13.00 13.40 b 9.90 10.10 c 13.00 13.40 d 9.90 10.10 e 0.80 f 0.30 g 1.90 2.20 h 2.70 i 0.25 0.50 j 0.73 0.93 k 0.10 0.20 l 0.10 0 7
rev. 1.20 180 ???? st 10 ? 2012 rev. 1.20 181 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver product tape and reel specifcations reel dimensions sop 24w (300mil), sop 28w (300mil) symbol description dimensions in mm ? reel o ? ter diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flan ? 24.8 +0.3/-0.2 t2 reel thickness 30.20.2 ssop 24s (150mil), ssop 28s (150mil) symbol description dimensions in mm ? reel o ? ter diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flan ? 16.8 +0.3/-0.2 t2 reel thickness 22.20.2
rev. 1.20 180 ????st 10? 2012 rev. 1.20 181 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver carrier tape dimensions

sop 24w symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation(width direction) 11.50.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation(len ? th direction) 2.00.1 ? 0 cavity len ? th 10.90.10 b0 cavity width 15.90.10 k0 cavity depth 3.10.1 t carrier tape thickness 0.350.05 c cover tape width 21.30.1 ssop 24s (150mil) symbol description dimensions in mm w carrier tape width 16.0 +0.3/-0.1 p cavity pitch 8.00.1 e perforation position 1.750.10 f cavity to perforation(width direction) 7.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation(len ? th direction) 2.00.1 ? 0 cavity len ? th 6.50.1 b0 cavity width 9.50.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1
rev. 1.20 182 ???? st 10 ? 2012 rev. 1.20 183 ????st 10? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation(width direction) 11.50.1 d perforation diameter 1.5 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation(len ? th direction) 2.00.1 ? 0 cavity len ? th 10.850.10 b0 cavity width 18.340.10 k0 cavity depth 2.970.10 t carrier tape thickness 0.350.01 c cover tape width 21.30.1 ssop 28s (150mil) symbol description dimensions in mm w carrier tape width 16.0+0.3 p cavity pitch 8.00.1 e perforation position 1.750.10 f cavity to perforation(width direction) 7.50.1 d perforation diameter 1.55 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation(len ? th direction) 2.00.1 ? 0 cavity len ? th 6.50.1 b0 cavity width 10.30.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1
rev. 1.20 182 ????st 10? 2012 rev. 1.20 183 ???? st 10 ? 2012 bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver bs85b12-3/bs85c20-3/bs85c20-5 touch key flash mcu with lcd/led driver holtek semiconductor inc. (headquarters) no.3 ? creation rd. ii ? science park ? hsinch ?? taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales offce) 4f-2 ? no. 3-2 ? y ? anq ? st. ? nankan ? software park ? taipei 115 ? taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales offce) 5f ? unit ?? prod ? ctivity b ? ildin ?? no.5 gaoxin m 2nd road ? nanshan district ? shenzhen ? china 518057 tel: 86-755-8616-9908 ? 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales offce) 46729 fremont blvd. ? fremont ? c ? 94538 ? us ? tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyri ? ht ? 2012 by holtek semiconductor inc. the information appearin ? in this data sheet is believed to be acc ? rate at the time of p ? blication. however ? holt ek ass ? mes no responsibility arisin ? from the ? se of the specifications described. the applications mentioned herein are ? sed solely for the p ? rpose of ill ? stration and holtek makes no warranty or representation that s ? ch applications will be s ? itable witho ? t f ? rther modification ? nor recommends the ? se of its prod ? cts for application that may present a risk to h ? man life d ? e to malf ? nction or otherwise. holtek's prod ? cts are not a ? thorized for ? se as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most ? p-to-date information ? please visit o ? r web site at http://www.holtek.com.tw .

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